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Artem-BArtem-B
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[NVPTX] expand trunc/ext on v2i32 (llvm#161715)
llvm#153478 made v2i32 legal on newer GPUs, but we can not lower all operations yet. Expand the `trunc/ext` operation until we implement efficient lowering.
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‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -638,6 +638,11 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
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// No support for these operations with v2f32/v2i32
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setOperationAction(ISD::INSERT_VECTOR_ELT, {MVT::v2f32, MVT::v2i32}, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, {MVT::v2f32, MVT::v2i32}, Expand);
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setOperationAction(ISD::TRUNCATE, MVT::v2i16, Expand);
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setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND},
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MVT::v2i32, Expand);
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// Need custom lowering in case the index is dynamic.
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if (STI.hasF32x2Instructions())
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, {MVT::v2f32, MVT::v2i32},

‎llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll‎

Lines changed: 145 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,5 +115,150 @@ define ptx_kernel void @inlineasm(ptr %p) {
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store <2 x float> %mul, ptr %p, align 8
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ret void
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}
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define ptx_kernel void @trunc_v2i32(<2 x i32> %0) {
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; CHECK-SM90A-LABEL: trunc_v2i32(
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; CHECK-SM90A: {
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; CHECK-SM90A-NEXT: .reg .b32 %r<7>;
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; CHECK-SM90A-NEXT: .reg .b64 %rd<2>;
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; CHECK-SM90A-EMPTY:
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; CHECK-SM90A-NEXT: // %bb.0:
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; CHECK-SM90A-NEXT: ld.param.v2.b32 {%r1, %r2}, [trunc_v2i32_param_0];
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; CHECK-SM90A-NEXT: prmt.b32 %r3, %r1, %r2, 0x3340U;
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; CHECK-SM90A-NEXT: mov.b32 %r4, 0;
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; CHECK-SM90A-NEXT: prmt.b32 %r5, %r4, 0, 0x3340U;
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; CHECK-SM90A-NEXT: prmt.b32 %r6, %r5, %r3, 0x5410U;
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; CHECK-SM90A-NEXT: mov.b64 %rd1, 0;
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; CHECK-SM90A-NEXT: st.b32 [%rd1], %r6;
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; CHECK-SM90A-NEXT: ret;
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;
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; CHECK-SM100-LABEL: trunc_v2i32(
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; CHECK-SM100: {
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; CHECK-SM100-NEXT: .reg .b32 %r<7>;
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; CHECK-SM100-NEXT: .reg .b64 %rd<3>;
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; CHECK-SM100-EMPTY:
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; CHECK-SM100-NEXT: // %bb.0:
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; CHECK-SM100-NEXT: ld.param.b64 %rd1, [trunc_v2i32_param_0];
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; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd1;
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; CHECK-SM100-NEXT: mov.b32 %r3, 0;
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; CHECK-SM100-NEXT: prmt.b32 %r4, %r3, 0, 0x3340U;
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; CHECK-SM100-NEXT: prmt.b32 %r5, %r1, %r2, 0x3340U;
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; CHECK-SM100-NEXT: prmt.b32 %r6, %r4, %r5, 0x5410U;
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; CHECK-SM100-NEXT: mov.b64 %rd2, 0;
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; CHECK-SM100-NEXT: st.b32 [%rd2], %r6;
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; CHECK-SM100-NEXT: ret;
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%2 = trunc <2 x i32> %0 to <2 x i8>
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%3 = shufflevector <2 x i8> zeroinitializer, <2 x i8> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i8> %3, ptr null, align 4
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ret void
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}
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define ptx_kernel void @zextend_to_v2i32(<2 x i8> %0) {
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; CHECK-SM90A-LABEL: zextend_to_v2i32(
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; CHECK-SM90A: {
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; CHECK-SM90A-NEXT: .reg .b16 %rs<3>;
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; CHECK-SM90A-NEXT: .reg .b32 %r<4>;
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; CHECK-SM90A-NEXT: .reg .b64 %rd<5>;
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; CHECK-SM90A-EMPTY:
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; CHECK-SM90A-NEXT: // %bb.0:
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; CHECK-SM90A-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [zextend_to_v2i32_param_0];
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; CHECK-SM90A-NEXT: mov.b32 %r1, {%rs1, %rs2};
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; CHECK-SM90A-NEXT: cvt.u32.u16 %r2, %rs1;
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; CHECK-SM90A-NEXT: cvt.u32.u16 %r3, %rs2;
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; CHECK-SM90A-NEXT: mov.b64 %rd1, 12;
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; CHECK-SM90A-NEXT: st.b32 [%rd1], %r3;
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; CHECK-SM90A-NEXT: mov.b64 %rd2, 8;
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; CHECK-SM90A-NEXT: st.b32 [%rd2], %r2;
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; CHECK-SM90A-NEXT: mov.b64 %rd3, 4;
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; CHECK-SM90A-NEXT: st.b32 [%rd3], 0;
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; CHECK-SM90A-NEXT: mov.b64 %rd4, 0;
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; CHECK-SM90A-NEXT: st.b32 [%rd4], 0;
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; CHECK-SM90A-NEXT: ret;
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;
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; CHECK-SM100-LABEL: zextend_to_v2i32(
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; CHECK-SM100: {
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; CHECK-SM100-NEXT: .reg .b16 %rs<3>;
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; CHECK-SM100-NEXT: .reg .b32 %r<5>;
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; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
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; CHECK-SM100-EMPTY:
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; CHECK-SM100-NEXT: // %bb.0:
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; CHECK-SM100-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [zextend_to_v2i32_param_0];
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; CHECK-SM100-NEXT: mov.b32 %r1, {%rs1, %rs2};
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; CHECK-SM100-NEXT: cvt.u32.u16 %r2, %rs2;
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; CHECK-SM100-NEXT: cvt.u32.u16 %r3, %rs1;
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; CHECK-SM100-NEXT: mov.b64 %rd1, {%r3, %r2};
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; CHECK-SM100-NEXT: mov.b32 %r4, 0;
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; CHECK-SM100-NEXT: mov.b64 %rd2, {%r4, %r4};
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; CHECK-SM100-NEXT: mov.b64 %rd3, 4;
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; CHECK-SM100-NEXT: st.b32 [%rd3], %rd2;
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; CHECK-SM100-NEXT: mov.b64 %rd4, 0;
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; CHECK-SM100-NEXT: st.b32 [%rd4], %rd2;
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; CHECK-SM100-NEXT: mov.b64 %rd5, 8;
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; CHECK-SM100-NEXT: st.b32 [%rd5], %rd1;
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; CHECK-SM100-NEXT: shr.u64 %rd6, %rd1, 32;
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; CHECK-SM100-NEXT: mov.b64 %rd7, 12;
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; CHECK-SM100-NEXT: st.b32 [%rd7], %rd6;
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; CHECK-SM100-NEXT: ret;
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%2 = zext <2 x i8> %0 to <2 x i32>
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%3 = shufflevector <2 x i32> zeroinitializer, <2 x i32> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i32> %3, ptr null, align 4
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ret void
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}
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define ptx_kernel void @sextend_to_v2i32(<2 x i8> %0) {
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; CHECK-SM90A-LABEL: sextend_to_v2i32(
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; CHECK-SM90A: {
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; CHECK-SM90A-NEXT: .reg .b16 %rs<3>;
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; CHECK-SM90A-NEXT: .reg .b32 %r<6>;
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; CHECK-SM90A-NEXT: .reg .b64 %rd<5>;
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; CHECK-SM90A-EMPTY:
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; CHECK-SM90A-NEXT: // %bb.0:
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; CHECK-SM90A-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [sextend_to_v2i32_param_0];
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; CHECK-SM90A-NEXT: mov.b32 %r1, {%rs1, %rs2};
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; CHECK-SM90A-NEXT: cvt.u32.u16 %r2, %rs1;
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; CHECK-SM90A-NEXT: cvt.s32.s8 %r3, %r2;
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; CHECK-SM90A-NEXT: cvt.u32.u16 %r4, %rs2;
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; CHECK-SM90A-NEXT: cvt.s32.s8 %r5, %r4;
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; CHECK-SM90A-NEXT: mov.b64 %rd1, 12;
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; CHECK-SM90A-NEXT: st.b32 [%rd1], %r5;
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; CHECK-SM90A-NEXT: mov.b64 %rd2, 8;
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; CHECK-SM90A-NEXT: st.b32 [%rd2], %r3;
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; CHECK-SM90A-NEXT: mov.b64 %rd3, 4;
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; CHECK-SM90A-NEXT: st.b32 [%rd3], 0;
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; CHECK-SM90A-NEXT: mov.b64 %rd4, 0;
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; CHECK-SM90A-NEXT: st.b32 [%rd4], 0;
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; CHECK-SM90A-NEXT: ret;
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;
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; CHECK-SM100-LABEL: sextend_to_v2i32(
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; CHECK-SM100: {
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; CHECK-SM100-NEXT: .reg .b16 %rs<3>;
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; CHECK-SM100-NEXT: .reg .b32 %r<7>;
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; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
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; CHECK-SM100-EMPTY:
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; CHECK-SM100-NEXT: // %bb.0:
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; CHECK-SM100-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [sextend_to_v2i32_param_0];
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; CHECK-SM100-NEXT: mov.b32 %r1, {%rs1, %rs2};
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; CHECK-SM100-NEXT: cvt.u32.u16 %r2, %rs2;
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; CHECK-SM100-NEXT: cvt.s32.s8 %r3, %r2;
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; CHECK-SM100-NEXT: cvt.u32.u16 %r4, %rs1;
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; CHECK-SM100-NEXT: cvt.s32.s8 %r5, %r4;
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; CHECK-SM100-NEXT: mov.b64 %rd1, {%r5, %r3};
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; CHECK-SM100-NEXT: mov.b32 %r6, 0;
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; CHECK-SM100-NEXT: mov.b64 %rd2, {%r6, %r6};
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; CHECK-SM100-NEXT: mov.b64 %rd3, 4;
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; CHECK-SM100-NEXT: st.b32 [%rd3], %rd2;
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; CHECK-SM100-NEXT: mov.b64 %rd4, 0;
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; CHECK-SM100-NEXT: st.b32 [%rd4], %rd2;
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; CHECK-SM100-NEXT: mov.b64 %rd5, 8;
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; CHECK-SM100-NEXT: st.b32 [%rd5], %rd1;
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; CHECK-SM100-NEXT: shr.u64 %rd6, %rd1, 32;
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; CHECK-SM100-NEXT: mov.b64 %rd7, 12;
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; CHECK-SM100-NEXT: st.b32 [%rd7], %rd6;
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; CHECK-SM100-NEXT: ret;
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%2 = sext <2 x i8> %0 to <2 x i32>
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%3 = shufflevector <2 x i32> zeroinitializer, <2 x i32> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i32> %3, ptr null, align 4
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ret void
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}

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