Skip to content

Commit d1f4f63

Browse files
uweiganduweigand
committed
[SystemZ] Use nop mnemonics for disassembly
To match the behavior of GNU binutils, output the nop family of mnemonic aliases when disassembling.
1 parent eb257fe commit d1f4f63

17 files changed

+89
-68
lines changed

‎lld/test/ELF/systemz-gotent-relax-und-dso.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,9 @@
1414
# DISASM: Disassembly of section .text:
1515
# DISASM-EMPTY:
1616
# DISASM-NEXT: <foo>:
17-
# DISASM-NEXT: nop 0
17+
# DISASM-NEXT: nop
1818
# DISASM: <hid>:
19-
# DISASM-NEXT: nop 0
19+
# DISASM-NEXT: nop
2020
# DISASM: <_start>:
2121
# DISASM-NEXT: lgrl %r1, 0x2400
2222
# DISASM-NEXT: lgrl %r1, 0x2400

‎lld/test/ELF/systemz-gotent-relax.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,9 @@
3030

3131
# DISASM: Disassembly of section .text:
3232
# DISASM: 00000000010011e0 <foo>:
33-
# DISASM-NEXT: nop 0
33+
# DISASM-NEXT: nop
3434
# DISASM: 00000000010011e4 <hid>:
35-
# DISASM-NEXT: nop 0
35+
# DISASM-NEXT: nop
3636
# DISASM: 00000000010011e8 <ifunc>:
3737
# DISASM-NEXT: br %r14
3838
# DISASM: 00000000010011ea <_start>:

‎lld/test/ELF/systemz-plt.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -48,9 +48,9 @@
4848
# DIS-NEXT: 100102c: d2 07 f0 30 10 08 mvc 48(8,%r15), 8(%r1)
4949
# DIS-NEXT: 1001032: e3 10 10 10 00 04 lg %r1, 16(%r1)
5050
# DIS-NEXT: 1001038: 07 f1 br %r1
51-
# DIS-NEXT: 100103a: 07 00 nopr %r0
52-
# DIS-NEXT: 100103c: 07 00 nopr %r0
53-
# DIS-NEXT: 100103e: 07 00 nopr %r0
51+
# DIS-NEXT: 100103a: 07 00 nopr
52+
# DIS-NEXT: 100103c: 07 00 nopr
53+
# DIS-NEXT: 100103e: 07 00 nopr
5454
# DIS-NEXT: 1001040: c0 10 00 00 10 54 larl %r1, 0x10030e8
5555
# DIS-NEXT: 1001046: e3 10 10 00 00 04 lg %r1, 0(%r1)
5656
# DIS-NEXT: 100104c: 07 f1 br %r1

‎lld/test/ELF/systemz-tls-gd.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58,17 +58,17 @@
5858

5959
## TP offset of a is at 0x1002218
6060
# LE-NEXT: lgrl %r2, 0x1002218
61-
# LE-NEXT: brcl 0,
61+
# LE-NEXT: jgnop
6262
# LE-NEXT: lgf %r2, 0(%r2,%r7)
6363

6464
## TP offset of b is at 0x1002220
6565
# LE-NEXT: lgrl %r2, 0x1002220
66-
# LE-NEXT: brcl 0,
66+
# LE-NEXT: jgnop
6767
# LE-NEXT: lgf %r2, 0(%r2,%r7)
6868

6969
## TP offset of c is at 0x1002228
7070
# LE-NEXT: lgrl %r2, 0x1002228
71-
# LE-NEXT: brcl 0,
71+
# LE-NEXT: jgnop
7272
# LE-NEXT: lgf %r2, 0(%r2,%r7)
7373

7474
## TP offsets
@@ -88,7 +88,7 @@
8888

8989
## TP offset of a is at 0x1002340
9090
# IE-NEXT: lgrl %r2, 0x1002340
91-
# IE-NEXT: brcl 0,
91+
# IE-NEXT: jgnop
9292
# IE-NEXT: lgf %r2, 0(%r2,%r7)
9393

9494
## GOT offset of the TP offset for b is at 0x1002348

‎lld/test/ELF/systemz-tls-ld.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949

5050
## GOT offset of the LDM TLS module ID is at 0x1002210
5151
# LE-NEXT: lgrl %r2, 0x1002210
52-
# LE-NEXT: brcl 0,
52+
# LE-NEXT: jgnop
5353
# LE-NEXT: la %r2, 0(%r2,%r7)
5454

5555
## TP offset for a is at 0x1002218

‎llvm/lib/Target/SystemZ/SystemZInstrFormats.td‎

Lines changed: 35 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2328,6 +2328,12 @@ class AsmCondBranchRI<string mnemonic, bits<12> opcode>
23282328
: InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
23292329
mnemonic#"\t$M1, $RI2", []>;
23302330

2331+
class NeverCondBranchRI<string mnemonic, bits<12> opcode>
2332+
: InstRIc<opcode, (outs), (ins brtarget16:$RI2),
2333+
mnemonic#"\t$RI2", []> {
2334+
let M1 = 0;
2335+
}
2336+
23312337
class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
23322338
SDPatternOperator operator = null_frag>
23332339
: InstRIc<opcode, (outs), (ins brtarget16:$RI2),
@@ -2347,6 +2353,12 @@ class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
23472353
: InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
23482354
mnemonic#"\t$M1, $RI2", []>;
23492355

2356+
class NeverCondBranchRIL<string mnemonic, bits<12> opcode>
2357+
: InstRILc<opcode, (outs), (ins brtarget32:$RI2),
2358+
mnemonic#"\t$RI2", []> {
2359+
let M1 = 0;
2360+
}
2361+
23502362
class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
23512363
: InstRILc<opcode, (outs), (ins brtarget32:$RI2),
23522364
!subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
@@ -2365,10 +2377,16 @@ class AsmCondBranchRR<string mnemonic, bits<8> opcode>
23652377
: InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
23662378
mnemonic#"\t$R1, $R2", []>;
23672379

2368-
class NeverCondBranchRR<string mnemonic, bits<8> opcode>
2369-
: InstRR<opcode, (outs), (ins GR64:$R2),
2370-
mnemonic#"\t$R2", []> {
2371-
let R1 = 0;
2380+
multiclass NeverCondBranchRR<string mnemonic, bits<8> opcode> {
2381+
// For the no-op (always false) branch, the target is optional.
2382+
def "" : InstRR<opcode, (outs), (ins GR64:$R2),
2383+
mnemonic#"\t$R2", []> {
2384+
let R1 = 0;
2385+
}
2386+
def Opt : InstRR<opcode, (outs), (ins), mnemonic, []> {
2387+
let R1 = 0;
2388+
let R2 = 0;
2389+
}
23722390
}
23732391

23742392
class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
@@ -2392,11 +2410,19 @@ class AsmCondBranchRX<string mnemonic, bits<8> opcode>
23922410
(ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
23932411
mnemonic#"\t$M1, $XBD2", []>;
23942412

2395-
class NeverCondBranchRX<string mnemonic, bits<8> opcode>
2396-
: InstRXb<opcode, (outs),
2397-
(ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2398-
mnemonic#"\t$XBD2", []> {
2399-
let M1 = 0;
2413+
multiclass NeverCondBranchRX<string mnemonic, bits<8> opcode> {
2414+
// For the no-op (always false) branch, the target is optional.
2415+
def "" : InstRXb<opcode, (outs),
2416+
(ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2417+
mnemonic#"\t$XBD2", []> {
2418+
let M1 = 0;
2419+
}
2420+
def Opt : InstRXb<opcode, (outs), (ins), mnemonic, []> {
2421+
let M1 = 0;
2422+
let B2 = 0;
2423+
let D2 = 0;
2424+
let X2 = 0;
2425+
}
24002426
}
24012427

24022428
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.td‎

Lines changed: 5 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -109,20 +109,11 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
109109
}
110110

111111
// NOPs. These are again variants of the conditional branches, with the
112-
// condition mask set to "never". NOP_bare can't be an InstAlias since it
113-
// would need R0D hard coded which is not part of ADDR64BitRegClass.
114-
def NOP : NeverCondBranchRX<"nop", 0x47>;
115-
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
116-
def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
117-
def NOPR : NeverCondBranchRR<"nopr", 0x07>;
118-
def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>;
119-
120-
// An alias of BRC 0, label
121-
def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>;
122-
123-
// An alias of BRCL 0, label
124-
// jgnop on gnu ; jlnop on hlasm
125-
def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>;
112+
// condition mask set to "never".
113+
defm NOP : NeverCondBranchRX<"nop", 0x47>;
114+
defm NOPR : NeverCondBranchRR<"nopr", 0x07>;
115+
def JNOP : NeverCondBranchRI<"jnop", 0xA74>;
116+
def JGNOP : NeverCondBranchRIL<"j{g|l}nop", 0xC04>;
126117

127118
// Fused compare-and-branch instructions.
128119
//

‎llvm/lib/Target/SystemZ/SystemZScheduleZ13.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1557,7 +1557,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
15571557
// NOPs
15581558
//===----------------------------------------------------------------------===//
15591559

1560-
def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
1561-
1560+
def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?(Opt)?$")>;
1561+
def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;
15621562
}
15631563

‎llvm/lib/Target/SystemZ/SystemZScheduleZ14.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1647,7 +1647,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
16471647
// NOPs
16481648
//===----------------------------------------------------------------------===//
16491649

1650-
def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
1651-
1650+
def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?(Opt)?$")>;
1651+
def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;
16521652
}
16531653

‎llvm/lib/Target/SystemZ/SystemZScheduleZ15.td‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1694,6 +1694,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
16941694
// NOPs
16951695
//===----------------------------------------------------------------------===//
16961696

1697-
def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
1697+
def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?(Opt)?$")>;
1698+
def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;
16981699
}
16991700

0 commit comments

Comments
 (0)