hardwired mtvec not supported, wrong test result #1
Description
Volume II: RISC-V Privileged Architectures V1.10 says in section 3.1.12: "The mtvec register must always be implemented, but can contain a hardwired read-only value."
Compliance test for RV32I however requires that mtvec is implemented and writeable.
This issue causes problems to comply with the competion rules, we must assume that we must not only comply with RV32I that allows hardwired mtvec, but also with unmodified test cases. So a clean implementation would require writeable mtvec for the RISCV contest 2018 rules.
Also any resource constrained RISCV implementation that use hardwired mtvec would fail on the compliance tests.