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maksyukimaksyuki
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feat: add csr reg
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‎rtl/tc_l3/src/main/scala/core/CSR.scala‎

Lines changed: 243 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,3 +87,246 @@ object CSR {
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mstatus
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)
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}
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object Cause {
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val InstAddrMisaligned = 0x0.U
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val IllegalInst = 0x2.U
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val Breakpoint = 0x3.U
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val LoadAddrMisaligned = 0x4.U
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val StoreAddrMisaligned = 0x6.U
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val Ecall = 0x8.U
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}
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class CSRIO(implicit p: Parameters) extends Bundle {
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val stall = Input(Bool())
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val cmd = Input(UInt(3.W))
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val in = Input(UInt(xlen.W))
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val out = Output(UInt(xlen.W))
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// excpetion
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val pc = Input(UInt(xlen.W))
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val addr = Input(UInt(xlen.W))
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val inst = Input(UInt(xlen.W))
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val illegal = Input(Bool())
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val st_type = Input(UInt(2.W))
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val ld_type = Input(UInt(3.W))
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val pc_check = Input(Bool())
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val expt = Output(Bool())
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val evec = Output(UInt(xlen.W))
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val epc = Output(UInt(xlen.W))
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// HTIF
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val host = new HostIO
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}
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class CSR(implicit val p: Parameters) extends Module {
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val io = IO(new CSRIO)
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val csr_addr = io.inst(31, 20)
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val rs1_addr = io.inst(19, 15)
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// user counters
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val time = RegInit(0.U(xlen.W))
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val timeh = RegInit(0.U(xlen.W))
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val cycle = RegInit(0.U(xlen.W))
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val cycleh = RegInit(0.U(xlen.W))
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val instret = RegInit(0.U(xlen.W))
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val instreth = RegInit(0.U(xlen.W))
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val mcpuid = Cat(
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0.U(2.W) /* RV32I */,
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0.U((xlen - 28).W),
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(1 << ('I' - 'A') /* Base ISA */ |
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1 << ('U' - 'A') /* User Mode */ ).U(26.W)
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)
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val mimpid = 0.U(xlen.W) // not implemented
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val mhartid = 0.U(xlen.W) // only one hart
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// interrupt enable stack
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val PRV = RegInit(CSR.PRV_M)
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val PRV1 = RegInit(CSR.PRV_M)
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val PRV2 = 0.U(2.W)
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val PRV3 = 0.U(2.W)
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val IE = RegInit(false.B)
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val IE1 = RegInit(false.B)
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val IE2 = false.B
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val IE3 = false.B
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// virtualization management field
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val VM = 0.U(5.W)
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// memory privilege
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val MPRV = false.B
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// extention context status
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val XS = 0.U(2.W)
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val FS = 0.U(2.W)
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val SD = 0.U(1.W)
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val mstatus = Cat(SD, 0.U((xlen - 23).W), VM, MPRV, XS, FS, PRV3, IE3, PRV2, IE2, PRV1, IE1, PRV, IE)
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val mtvec = Const.PC_EVEC.U(xlen.W)
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val mtdeleg = 0x0.U(xlen.W)
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// interrupt registers
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val MTIP = RegInit(false.B)
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val HTIP = false.B
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val STIP = false.B
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val MTIE = RegInit(false.B)
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val HTIE = false.B
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val STIE = false.B
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val MSIP = RegInit(false.B)
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val HSIP = false.B
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val SSIP = false.B
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val MSIE = RegInit(false.B)
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val HSIE = false.B
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val SSIE = false.B
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val mip = Cat(0.U((xlen - 8).W), MTIP, HTIP, STIP, false.B, MSIP, HSIP, SSIP, false.B)
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val mie = Cat(0.U((xlen - 8).W), MTIE, HTIE, STIE, false.B, MSIE, HSIE, SSIE, false.B)
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val mtimecmp = Reg(UInt(xlen.W))
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val mscratch = Reg(UInt(xlen.W))
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val mepc = Reg(UInt(xlen.W))
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val mcause = Reg(UInt(xlen.W))
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val mbadaddr = Reg(UInt(xlen.W))
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val mtohost = RegInit(0.U(xlen.W))
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val mfromhost = Reg(UInt(xlen.W))
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io.host.tohost := mtohost
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when(io.host.fromhost.valid) {
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mfromhost := io.host.fromhost.bits
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}
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val csrFile = Seq(
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BitPat(CSR.cycle) -> cycle,
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BitPat(CSR.time) -> time,
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BitPat(CSR.instret) -> instret,
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BitPat(CSR.cycleh) -> cycleh,
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BitPat(CSR.timeh) -> timeh,
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BitPat(CSR.instreth) -> instreth,
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BitPat(CSR.cyclew) -> cycle,
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BitPat(CSR.timew) -> time,
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BitPat(CSR.instretw) -> instret,
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BitPat(CSR.cyclehw) -> cycleh,
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BitPat(CSR.timehw) -> timeh,
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BitPat(CSR.instrethw) -> instreth,
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BitPat(CSR.mcpuid) -> mcpuid,
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BitPat(CSR.mimpid) -> mimpid,
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BitPat(CSR.mhartid) -> mhartid,
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BitPat(CSR.mtvec) -> mtvec,
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BitPat(CSR.mtdeleg) -> mtdeleg,
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BitPat(CSR.mie) -> mie,
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BitPat(CSR.mtimecmp) -> mtimecmp,
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BitPat(CSR.mtime) -> time,
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BitPat(CSR.mtimeh) -> timeh,
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BitPat(CSR.mscratch) -> mscratch,
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BitPat(CSR.mepc) -> mepc,
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BitPat(CSR.mcause) -> mcause,
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BitPat(CSR.mbadaddr) -> mbadaddr,
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BitPat(CSR.mip) -> mip,
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BitPat(CSR.mtohost) -> mtohost,
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BitPat(CSR.mfromhost) -> mfromhost,
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BitPat(CSR.mstatus) -> mstatus
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)
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io.out := Lookup(csr_addr, 0.U, csrFile).asUInt
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val privValid = csr_addr(9, 8) <= PRV
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val privInst = io.cmd === CSR.P
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val isEcall = privInst && !csr_addr(0) && !csr_addr(8)
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val isEbreak = privInst && csr_addr(0) && !csr_addr(8)
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val isEret = privInst && !csr_addr(0) && csr_addr(8)
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val csrValid = csrFile.map(_._1 === csr_addr).reduce(_ || _)
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val csrRO = csr_addr(11, 10).andR || csr_addr === CSR.mtvec || csr_addr === CSR.mtdeleg
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val wen = io.cmd === CSR.W || io.cmd(1) && rs1_addr.orR
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val wdata = MuxLookup(
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io.cmd,
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0.U,
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Seq(
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CSR.W -> io.in,
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CSR.S -> (io.out | io.in),
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CSR.C -> (io.out & ~io.in)
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)
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)
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val iaddrInvalid = io.pc_check && io.addr(1)
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val laddrInvalid = MuxLookup(
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io.ld_type,
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false.B,
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Seq(
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Control.LD_LW -> io.addr(1, 0).orR,
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Control.LD_LH -> io.addr(0),
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Control.LD_LHU -> io.addr(0)
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)
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)
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val saddrInvalid = MuxLookup(
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io.st_type,
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false.B,
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Seq(
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Control.ST_SW -> io.addr(1, 0).orR,
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Control.ST_SH -> io.addr(0)
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)
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)
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io.expt := io.illegal || iaddrInvalid || laddrInvalid || saddrInvalid ||
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io.cmd(1, 0).orR && (!csrValid || !privValid) || wen && csrRO ||
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(privInst && !privValid) || isEcall || isEbreak
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io.evec := mtvec + (PRV << 6)
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io.epc := mepc
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// Counters
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time := time + 1.U
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when(time.andR) { timeh := timeh + 1.U }
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cycle := cycle + 1.U
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when(cycle.andR) { cycleh := cycleh + 1.U }
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val isInstRet = io.inst =/= Instructions.NOP && (!io.expt || isEcall || isEbreak) && !io.stall
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when(isInstRet) { instret := instret + 1.U }
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when(isInstRet && instret.andR) { instreth := instreth + 1.U }
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when(!io.stall) {
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when(io.expt) {
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mepc := io.pc >> 2 << 2
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mcause := Mux(
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iaddrInvalid,
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Cause.InstAddrMisaligned,
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Mux(
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laddrInvalid,
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Cause.LoadAddrMisaligned,
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Mux(saddrInvalid, Cause.StoreAddrMisaligned, Mux(isEcall, Cause.Ecall + PRV, Mux(isEbreak, Cause.Breakpoint, Cause.IllegalInst)))
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)
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)
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PRV := CSR.PRV_M
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IE := false.B
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PRV1 := PRV
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IE1 := IE
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when(iaddrInvalid || laddrInvalid || saddrInvalid) { mbadaddr := io.addr }
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}.elsewhen(isEret) {
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PRV := PRV1
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IE := IE1
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PRV1 := CSR.PRV_U
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IE1 := true.B
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}.elsewhen(wen) {
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when(csr_addr === CSR.mstatus) {
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PRV1 := wdata(5, 4)
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IE1 := wdata(3)
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PRV := wdata(2, 1)
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IE := wdata(0)
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}.elsewhen(csr_addr === CSR.mip) {
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MTIP := wdata(7)
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MSIP := wdata(3)
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}.elsewhen(csr_addr === CSR.mie) {
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MTIE := wdata(7)
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MSIE := wdata(3)
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}.elsewhen(csr_addr === CSR.mtime) { time := wdata }
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.elsewhen(csr_addr === CSR.mtimeh) { timeh := wdata }
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.elsewhen(csr_addr === CSR.mtimecmp) { mtimecmp := wdata }
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.elsewhen(csr_addr === CSR.mscratch) { mscratch := wdata }
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.elsewhen(csr_addr === CSR.mepc) { mepc := wdata >> 2.U << 2.U }
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.elsewhen(csr_addr === CSR.mcause) { mcause := wdata & (BigInt(1) << (xlen - 1) | 0xf).U }
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.elsewhen(csr_addr === CSR.mbadaddr) { mbadaddr := wdata }
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.elsewhen(csr_addr === CSR.mtohost) { mtohost := wdata }
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.elsewhen(csr_addr === CSR.mfromhost) { mfromhost := wdata }
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.elsewhen(csr_addr === CSR.cyclew) { cycle := wdata }
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.elsewhen(csr_addr === CSR.timew) { time := wdata }
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.elsewhen(csr_addr === CSR.instretw) { instret := wdata }
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.elsewhen(csr_addr === CSR.cyclehw) { cycleh := wdata }
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.elsewhen(csr_addr === CSR.timehw) { timeh := wdata }
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.elsewhen(csr_addr === CSR.instrethw) { instreth := wdata }
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}
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}
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}

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