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maksyukimaksyuki
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style: change crlf to lf format
1 parent 01616ed commit 2f3b3c9

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12 files changed

+671
-668
lines changed

12 files changed

+671
-668
lines changed

‎rtl/tc_l2/src/main/scala/axi4/Crossbar.scala‎

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1,60 +1,60 @@
1-
package treecorel2
2-
3-
import chisel3._
4-
import chisel3.util._
5-
6-
class Crossbar extends Module {
7-
val io = IO(new Bundle {
8-
val socEn = Input(Bool())
9-
val runEn = Input(Bool())
10-
val dxchg = new DXCHGIO
11-
val core = new COREIO
12-
})
13-
14-
protected val globalEn = RegInit(false.B)
15-
protected val inst = RegInit(0.U(32.W))
16-
protected val rdInst = Mux(io.core.fetch.addr(2).asBool(), io.dxchg.rdata(63, 32), io.dxchg.rdata(31, 0))
17-
18-
io.core.globalEn := Mux(io.runEn, globalEn, false.B)
19-
io.core.fetch.data := inst
20-
io.core.ld.data := io.dxchg.rdata
21-
22-
// FSM for inst or mem data xform
23-
protected val eumInst :: eumMem :: Nil = Enum(2)
24-
protected val stateReg = RegInit(eumInst)
25-
26-
switch(stateReg) {
27-
is(eumInst) {
28-
when(io.runEn) {
29-
stateReg := eumMem
30-
globalEn := true.B
31-
inst := rdInst
32-
}
33-
}
34-
is(eumMem) {
35-
when(io.runEn) {
36-
stateReg := eumInst
37-
globalEn := false.B
38-
inst := 0x13.U
39-
}
40-
}
41-
}
42-
43-
protected val instSize = Mux(io.socEn, 2.U, 3.U)
44-
// because the difftest's logic addr is 0x000000
45-
protected val addrOffset = Mux(io.socEn, "h0000000000000000".U(64.W), "h0000000080000000".U(64.W))
46-
47-
protected val instAddr = io.core.fetch.addr - addrOffset
48-
protected val loadAddr = io.core.ld.addr - addrOffset
49-
protected val storeAddr = io.core.sd.addr - addrOffset
50-
protected val maEn = io.core.ld.en || io.core.sd.en
51-
52-
io.dxchg.clk := clock
53-
io.dxchg.ren := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
54-
io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, loadAddr)
55-
io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
56-
io.dxchg.waddr := storeAddr
57-
io.dxchg.wdata := io.core.sd.data
58-
io.dxchg.wmask := io.core.sd.mask
59-
io.dxchg.wen := stateReg === eumMem && io.core.sd.en
60-
}
1+
package treecorel2
2+
3+
import chisel3._
4+
import chisel3.util._
5+
6+
class Crossbar extends Module {
7+
val io = IO(new Bundle {
8+
val socEn = Input(Bool())
9+
val runEn = Input(Bool())
10+
val dxchg = new DXCHGIO
11+
val core = new COREIO
12+
})
13+
14+
protected val globalEn = RegInit(false.B)
15+
protected val inst = RegInit(0.U(32.W))
16+
protected val rdInst = Mux(io.core.fetch.addr(2).asBool(), io.dxchg.rdata(63, 32), io.dxchg.rdata(31, 0))
17+
18+
io.core.globalEn := Mux(io.runEn, globalEn, false.B)
19+
io.core.fetch.data := inst
20+
io.core.ld.data := io.dxchg.rdata
21+
22+
// FSM for inst or mem data xform
23+
protected val eumInst :: eumMem :: Nil = Enum(2)
24+
protected val stateReg = RegInit(eumInst)
25+
26+
switch(stateReg) {
27+
is(eumInst) {
28+
when(io.runEn) {
29+
stateReg := eumMem
30+
globalEn := true.B
31+
inst := rdInst
32+
}
33+
}
34+
is(eumMem) {
35+
when(io.runEn) {
36+
stateReg := eumInst
37+
globalEn := false.B
38+
inst := 0x13.U
39+
}
40+
}
41+
}
42+
43+
protected val instSize = Mux(io.socEn, 2.U, 3.U)
44+
// because the difftest's logic addr is 0x000000
45+
protected val addrOffset = Mux(io.socEn, "h0000000000000000".U(64.W), "h0000000080000000".U(64.W))
46+
47+
protected val instAddr = io.core.fetch.addr - addrOffset
48+
protected val loadAddr = io.core.ld.addr - addrOffset
49+
protected val storeAddr = io.core.sd.addr - addrOffset
50+
protected val maEn = io.core.ld.en || io.core.sd.en
51+
52+
io.dxchg.clk := clock
53+
io.dxchg.ren := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
54+
io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, loadAddr)
55+
io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
56+
io.dxchg.waddr := storeAddr
57+
io.dxchg.wdata := io.core.sd.data
58+
io.dxchg.wmask := io.core.sd.mask
59+
io.dxchg.wen := stateReg === eumMem && io.core.sd.en
60+
}

‎rtl/tc_l2/src/main/scala/core/Processor.scala‎

Lines changed: 41 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1,41 +1,41 @@
1-
package sim
2-
3-
import chisel3._
4-
import chisel3.util._
5-
6-
import difftest._
7-
import treecorel2._
8-
9-
class Processor extends Module {
10-
val io = IO(new Bundle {
11-
val runEn = Input(Bool())
12-
val socEn = Input(Bool())
13-
val dxchg = new DXCHGIO
14-
val instComm = Flipped(new DiffInstrCommitIO)
15-
val archIntRegState = Flipped(new DiffArchIntRegStateIO)
16-
val csrState = Flipped(new DiffCSRStateIO)
17-
val trapEvt = Flipped(new DiffTrapEventIO)
18-
val archFpRegState = Flipped(new DiffArchFpRegStateIO)
19-
val archEvt = Flipped(new DiffArchEventIO)
20-
})
21-
22-
protected val cpu = Module(new TreeCoreL2)
23-
protected val crossbar = Module(new Crossbar)
24-
25-
cpu.io.socEn := io.socEn
26-
crossbar.io.runEn := io.runEn
27-
crossbar.io.socEn := io.socEn
28-
29-
cpu.io.globalEn <> crossbar.io.core.globalEn
30-
cpu.io.fetch <> crossbar.io.core.fetch
31-
cpu.io.ld <> crossbar.io.core.ld
32-
cpu.io.sd <> crossbar.io.core.sd
33-
crossbar.io.dxchg <> io.dxchg
34-
35-
cpu.io.instComm <> io.instComm
36-
cpu.io.archIntRegState <> io.archIntRegState
37-
cpu.io.csrState <> io.csrState
38-
cpu.io.trapEvt <> io.trapEvt
39-
cpu.io.archFpRegState <> io.archFpRegState
40-
cpu.io.archEvt <> io.archEvt
41-
}
1+
package sim
2+
3+
import chisel3._
4+
import chisel3.util._
5+
6+
import difftest._
7+
import treecorel2._
8+
9+
class Processor extends Module {
10+
val io = IO(new Bundle {
11+
val runEn = Input(Bool())
12+
val socEn = Input(Bool())
13+
val dxchg = new DXCHGIO
14+
val instComm = Flipped(new DiffInstrCommitIO)
15+
val archIntRegState = Flipped(new DiffArchIntRegStateIO)
16+
val csrState = Flipped(new DiffCSRStateIO)
17+
val trapEvt = Flipped(new DiffTrapEventIO)
18+
val archFpRegState = Flipped(new DiffArchFpRegStateIO)
19+
val archEvt = Flipped(new DiffArchEventIO)
20+
})
21+
22+
protected val cpu = Module(new TreeCoreL2)
23+
protected val crossbar = Module(new Crossbar)
24+
25+
cpu.io.socEn := io.socEn
26+
crossbar.io.runEn := io.runEn
27+
crossbar.io.socEn := io.socEn
28+
29+
cpu.io.globalEn <> crossbar.io.core.globalEn
30+
cpu.io.fetch <> crossbar.io.core.fetch
31+
cpu.io.ld <> crossbar.io.core.ld
32+
cpu.io.sd <> crossbar.io.core.sd
33+
crossbar.io.dxchg <> io.dxchg
34+
35+
cpu.io.instComm <> io.instComm
36+
cpu.io.archIntRegState <> io.archIntRegState
37+
cpu.io.csrState <> io.csrState
38+
cpu.io.trapEvt <> io.trapEvt
39+
cpu.io.archFpRegState <> io.archFpRegState
40+
cpu.io.archEvt <> io.archEvt
41+
}

‎rtl/tc_l2/src/main/scala/core/exec/ALU.scala‎

Lines changed: 53 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -1,53 +1,53 @@
1-
package treecorel2
2-
3-
import chisel3._
4-
import chisel3.util._
5-
6-
class ALU extends Module {
7-
val io = IO(new Bundle {
8-
val isa = Input(new ISAIO)
9-
val src1 = Input(UInt(64.W))
10-
val src2 = Input(UInt(64.W))
11-
val imm = Input(new IMMIO)
12-
val res = Output(UInt(64.W))
13-
})
14-
15-
protected val addi = SignExt(io.isa.ADDI.asUInt, 64) & (io.src1 + io.imm.I)
16-
protected val add = SignExt(io.isa.ADD.asUInt, 64) & (io.src1 + io.src2)
17-
protected val lui = SignExt(io.isa.LUI.asUInt, 64) & (io.imm.U)
18-
protected val sub = SignExt(io.isa.SUB.asUInt, 64) & (io.src1 - io.src2)
19-
protected val addiw = SignExt(io.isa.ADDIW.asUInt, 64) & SignExt((io.src1 + io.imm.I)(31, 0), 64)
20-
protected val addw = SignExt(io.isa.ADDW.asUInt, 64) & SignExt((io.src1 + io.src2)(31, 0), 64)
21-
protected val subw = SignExt(io.isa.SUBW.asUInt, 64) & SignExt((io.src1 - io.src2)(31, 0), 64)
22-
protected val arith = addi | add | lui | sub | addiw | addw | subw
23-
24-
protected val andi = SignExt(io.isa.ANDI.asUInt, 64) & (io.src1 & io.imm.I)
25-
protected val and = SignExt(io.isa.AND.asUInt, 64) & (io.src1 & io.src2)
26-
protected val ori = SignExt(io.isa.ORI.asUInt, 64) & (io.src1 | io.imm.I)
27-
protected val or = SignExt(io.isa.OR.asUInt, 64) & (io.src1 | io.src2)
28-
protected val xori = SignExt(io.isa.XORI.asUInt, 64) & (io.src1 ^ io.imm.I)
29-
protected val xor = SignExt(io.isa.XOR.asUInt, 64) & (io.src1 ^ io.src2)
30-
protected val logc = andi | and | ori | or | xori | xor
31-
32-
protected val slt = Mux((io.isa.SLT && (io.src1.asSInt < io.src2.asSInt)), 1.U(64.W), 0.U(64.W))
33-
protected val slti = Mux((io.isa.SLTI && (io.src1.asSInt < io.imm.I.asSInt)), 1.U(64.W), 0.U(64.W))
34-
protected val sltu = Mux((io.isa.SLTU && (io.src1.asUInt < io.src2.asUInt)), 1.U(64.W), 0.U(64.W))
35-
protected val sltiu = Mux((io.isa.SLTIU && (io.src1.asUInt < io.imm.I.asUInt)), 1.U(64.W), 0.U(64.W))
36-
protected val comp = slt | slti | sltu | sltiu
37-
38-
protected val sll = SignExt(io.isa.SLL.asUInt, 64) & (io.src1 << io.src2(5, 0))(63, 0)
39-
protected val srl = SignExt(io.isa.SRL.asUInt, 64) & (io.src1 >> io.src2(5, 0))
40-
protected val sra = SignExt(io.isa.SRA.asUInt, 64) & (io.src1.asSInt >> io.src2(5, 0)).asUInt
41-
protected val slli = SignExt(io.isa.SLLI.asUInt, 64) & (io.src1 << io.imm.I(5, 0))(63, 0)
42-
protected val srli = SignExt(io.isa.SRLI.asUInt, 64) & (io.src1 >> io.imm.I(5, 0))
43-
protected val srai = SignExt(io.isa.SRAI.asUInt, 64) & (io.src1.asSInt >> io.imm.I(5, 0)).asUInt
44-
protected val sllw = SignExt(io.isa.SLLW.asUInt, 64) & SignExt((io.src1 << io.src2(4, 0))(31, 0), 64)
45-
protected val srlw = SignExt(io.isa.SRLW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.src2(4, 0)), 64)
46-
protected val sraw = SignExt(io.isa.SRAW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.src2(4, 0)).asUInt, 64)
47-
protected val slliw = SignExt(io.isa.SLLIW.asUInt, 64) & SignExt((io.src1 << io.imm.I(4, 0))(31, 0), 64)
48-
protected val srliw = SignExt(io.isa.SRLIW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.imm.I(4, 0)), 64)
49-
protected val sraiw = SignExt(io.isa.SRAIW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.imm.I(4, 0)).asUInt, 64)
50-
protected val shift = sll | srl | sra | slli | srli | srai | sllw | srlw | sraw | slliw | srliw | sraiw
51-
52-
io.res := arith | logc | comp | shift
53-
}
1+
package treecorel2
2+
3+
import chisel3._
4+
import chisel3.util._
5+
6+
class ALU extends Module {
7+
val io = IO(new Bundle {
8+
val isa = Input(new ISAIO)
9+
val src1 = Input(UInt(64.W))
10+
val src2 = Input(UInt(64.W))
11+
val imm = Input(new IMMIO)
12+
val res = Output(UInt(64.W))
13+
})
14+
15+
protected val addi = SignExt(io.isa.ADDI.asUInt, 64) & (io.src1 + io.imm.I)
16+
protected val add = SignExt(io.isa.ADD.asUInt, 64) & (io.src1 + io.src2)
17+
protected val lui = SignExt(io.isa.LUI.asUInt, 64) & (io.imm.U)
18+
protected val sub = SignExt(io.isa.SUB.asUInt, 64) & (io.src1 - io.src2)
19+
protected val addiw = SignExt(io.isa.ADDIW.asUInt, 64) & SignExt((io.src1 + io.imm.I)(31, 0), 64)
20+
protected val addw = SignExt(io.isa.ADDW.asUInt, 64) & SignExt((io.src1 + io.src2)(31, 0), 64)
21+
protected val subw = SignExt(io.isa.SUBW.asUInt, 64) & SignExt((io.src1 - io.src2)(31, 0), 64)
22+
protected val arith = addi | add | lui | sub | addiw | addw | subw
23+
24+
protected val andi = SignExt(io.isa.ANDI.asUInt, 64) & (io.src1 & io.imm.I)
25+
protected val and = SignExt(io.isa.AND.asUInt, 64) & (io.src1 & io.src2)
26+
protected val ori = SignExt(io.isa.ORI.asUInt, 64) & (io.src1 | io.imm.I)
27+
protected val or = SignExt(io.isa.OR.asUInt, 64) & (io.src1 | io.src2)
28+
protected val xori = SignExt(io.isa.XORI.asUInt, 64) & (io.src1 ^ io.imm.I)
29+
protected val xor = SignExt(io.isa.XOR.asUInt, 64) & (io.src1 ^ io.src2)
30+
protected val logc = andi | and | ori | or | xori | xor
31+
32+
protected val slt = Mux((io.isa.SLT && (io.src1.asSInt < io.src2.asSInt)), 1.U(64.W), 0.U(64.W))
33+
protected val slti = Mux((io.isa.SLTI && (io.src1.asSInt < io.imm.I.asSInt)), 1.U(64.W), 0.U(64.W))
34+
protected val sltu = Mux((io.isa.SLTU && (io.src1.asUInt < io.src2.asUInt)), 1.U(64.W), 0.U(64.W))
35+
protected val sltiu = Mux((io.isa.SLTIU && (io.src1.asUInt < io.imm.I.asUInt)), 1.U(64.W), 0.U(64.W))
36+
protected val comp = slt | slti | sltu | sltiu
37+
38+
protected val sll = SignExt(io.isa.SLL.asUInt, 64) & (io.src1 << io.src2(5, 0))(63, 0)
39+
protected val srl = SignExt(io.isa.SRL.asUInt, 64) & (io.src1 >> io.src2(5, 0))
40+
protected val sra = SignExt(io.isa.SRA.asUInt, 64) & (io.src1.asSInt >> io.src2(5, 0)).asUInt
41+
protected val slli = SignExt(io.isa.SLLI.asUInt, 64) & (io.src1 << io.imm.I(5, 0))(63, 0)
42+
protected val srli = SignExt(io.isa.SRLI.asUInt, 64) & (io.src1 >> io.imm.I(5, 0))
43+
protected val srai = SignExt(io.isa.SRAI.asUInt, 64) & (io.src1.asSInt >> io.imm.I(5, 0)).asUInt
44+
protected val sllw = SignExt(io.isa.SLLW.asUInt, 64) & SignExt((io.src1 << io.src2(4, 0))(31, 0), 64)
45+
protected val srlw = SignExt(io.isa.SRLW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.src2(4, 0)), 64)
46+
protected val sraw = SignExt(io.isa.SRAW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.src2(4, 0)).asUInt, 64)
47+
protected val slliw = SignExt(io.isa.SLLIW.asUInt, 64) & SignExt((io.src1 << io.imm.I(4, 0))(31, 0), 64)
48+
protected val srliw = SignExt(io.isa.SRLIW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.imm.I(4, 0)), 64)
49+
protected val sraiw = SignExt(io.isa.SRAIW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.imm.I(4, 0)).asUInt, 64)
50+
protected val shift = sll | srl | sra | slli | srli | srai | sllw | srlw | sraw | slliw | srliw | sraiw
51+
52+
io.res := arith | logc | comp | shift
53+
}

‎rtl/tc_l2/src/main/scala/core/exec/BEU.scala‎

Lines changed: 41 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1,41 +1,41 @@
1-
package treecorel2
2-
3-
import chisel3._
4-
import chisel3.util._
5-
6-
class BEU extends Module {
7-
val io = IO(new Bundle {
8-
val isa = Input(new ISAIO)
9-
val imm = Input(new IMMIO)
10-
val src1 = Input(UInt(64.W))
11-
val src2 = Input(UInt(64.W))
12-
val pc = Input(UInt(64.W))
13-
val branch = Output(Bool())
14-
val tgt = Output(UInt(64.W))
15-
})
16-
17-
protected val beq = io.isa.BEQ && (io.src1 === io.src2)
18-
protected val bne = io.isa.BNE && (io.src1 =/= io.src2)
19-
protected val bgeu = io.isa.BGEU && (io.src1 >= io.src2)
20-
protected val bltu = io.isa.BLTU && (io.src1 < io.src2)
21-
protected val bge = io.isa.BGE && (io.src1.asSInt >= io.src2.asSInt)
22-
protected val blt = io.isa.BLT && (io.src1.asSInt < io.src2.asSInt)
23-
protected val b = beq | bne | bgeu | bltu | bge | blt
24-
25-
protected val jal = io.isa.JAL
26-
protected val jalr = io.isa.JALR
27-
28-
protected val b_tgt = io.pc + io.imm.B
29-
protected val jal_tgt = io.pc + io.imm.J
30-
protected val jalr_tgt = io.src1 + io.imm.I
31-
32-
io.branch := b | jal | jalr
33-
34-
when(jal) {
35-
io.tgt := jal_tgt
36-
}.elsewhen(jalr) {
37-
io.tgt := jalr_tgt
38-
}.otherwise {
39-
io.tgt := b_tgt
40-
}
41-
}
1+
package treecorel2
2+
3+
import chisel3._
4+
import chisel3.util._
5+
6+
class BEU extends Module {
7+
val io = IO(new Bundle {
8+
val isa = Input(new ISAIO)
9+
val imm = Input(new IMMIO)
10+
val src1 = Input(UInt(64.W))
11+
val src2 = Input(UInt(64.W))
12+
val pc = Input(UInt(64.W))
13+
val branch = Output(Bool())
14+
val tgt = Output(UInt(64.W))
15+
})
16+
17+
protected val beq = io.isa.BEQ && (io.src1 === io.src2)
18+
protected val bne = io.isa.BNE && (io.src1 =/= io.src2)
19+
protected val bgeu = io.isa.BGEU && (io.src1 >= io.src2)
20+
protected val bltu = io.isa.BLTU && (io.src1 < io.src2)
21+
protected val bge = io.isa.BGE && (io.src1.asSInt >= io.src2.asSInt)
22+
protected val blt = io.isa.BLT && (io.src1.asSInt < io.src2.asSInt)
23+
protected val b = beq | bne | bgeu | bltu | bge | blt
24+
25+
protected val jal = io.isa.JAL
26+
protected val jalr = io.isa.JALR
27+
28+
protected val b_tgt = io.pc + io.imm.B
29+
protected val jal_tgt = io.pc + io.imm.J
30+
protected val jalr_tgt = io.src1 + io.imm.I
31+
32+
io.branch := b | jal | jalr
33+
34+
when(jal) {
35+
io.tgt := jal_tgt
36+
}.elsewhen(jalr) {
37+
io.tgt := jalr_tgt
38+
}.otherwise {
39+
io.tgt := b_tgt
40+
}
41+
}

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