refactor: add io and inst trait config to share common vars

Author: maksyuki

rtl/tc_l3/src/main/scala/core/ex/ALU.scala

@@ -20,24 +20,24 @@ object ALU {
   val ALU_XXX    = 15.U(ALUOperLen.W)
 }
 
-class ALUIO(implicit p: Parameters) extends Bundle {
-  val A      = Input(UInt(xlen.W))
-  val B      = Input(UInt(xlen.W))
+class ALUIO extends Bundle with IOConfig {
+  val A      = Input(UInt(XLen.W))
+  val B      = Input(UInt(XLen.W))
   val alu_op = Input(UInt(4.W))
-  val out    = Output(UInt(xlen.W))
-  val sum    = Output(UInt(xlen.W))
+  val out    = Output(UInt(XLen.W))
+  val sum    = Output(UInt(XLen.W))
 }
 
-class ALU(implicit p: Parameters) extends Module {
-  val io     = IO(new ALUIO)
-  val sum    = io.A + Mux(io.alu_op(0), -io.B, io.B)
-  val cmp    = Mux(io.A(xlen - 1) === io.B(xlen - 1), sum(xlen - 1), Mux(io.alu_op(1), io.B(xlen - 1), io.A(xlen - 1)))
-  val shamt  = io.B(4, 0).asUInt
-  val shin   = Mux(io.alu_op(3), io.A, Reverse(io.A))
-  val shiftr = (Cat(io.alu_op(0) && shin(xlen - 1), shin).asSInt >> shamt)(xlen - 1, 0)
-  val shiftl = Reverse(shiftr)
+class ALU extends Module with InstConfig {
+  val io               = IO(new ALUIO)
+  protected val sum    = io.A + Mux(io.alu_op(0), -io.B, io.B)
+  protected val cmp    = Mux(io.A(XLen - 1) === io.B(XLen - 1), sum(XLen - 1), Mux(io.alu_op(1), io.B(XLen - 1), io.A(XLen - 1)))
+  protected val shamt  = io.B(4, 0).asUInt
+  protected val shin   = Mux(io.alu_op(3), io.A, Reverse(io.A))
+  protected val shiftr = (Cat(io.alu_op(0) && shin(XLen - 1), shin).asSInt >> shamt)(XLen - 1, 0)
+  protected val shiftl = Reverse(shiftr)
 
-  val out = MuxLookup(
+  protected val out = MuxLookup(
     io.alu_op,
     io.B,
     Seq(

rtl/tc_l3/src/main/scala/core/ex/BrCond.scala

@@ -3,23 +3,23 @@ package treecorel3
 import chisel._
 import chisel.uitl._
 
-class BrCondIO(implicit p: Parameters) extends CoreBundle()(p) {
-  val rs1     = Input(UInt(xlen.W))
-  val rs2     = Input(UInt(xlen.W))
+class BrCondIO extends Bundle with IOConfig {
+  val rs1     = Input(UInt(XLen.W))
+  val rs2     = Input(UInt(XLen.W))
   val br_type = Input(UInt(3.W))
   val taken   = Output(Bool())
 }
 
-class BrCond(implicit val p: Parameters) extends Module {
-  val io         = IO(new BrCondIO)
-  val diff       = io.rs1 - io.rs2
-  val neq        = diff.orR
-  val eq         = !neq
-  val isSameSign = io.rs1(xlen - 1) === io.rs2(xlen - 1)
-  val lt         = Mux(isSameSign, diff(xlen - 1), io.rs1(xlen - 1))
-  val ltu        = Mux(isSameSign, diff(xlen - 1), io.rs2(xlen - 1))
-  val ge         = !lt
-  val geu        = !ltu
+class BrCond extends Module with InstConfig {
+  val io                   = IO(new BrCondIO)
+  protected val diff       = io.rs1 - io.rs2
+  protected val neq        = diff.orR
+  protected val eq         = !neq
+  protected val isSameSign = io.rs1(XLen - 1) === io.rs2(XLen - 1)
+  protected val lt         = Mux(isSameSign, diff(XLen - 1), io.rs1(XLen - 1))
+  protected val ltu        = Mux(isSameSign, diff(XLen - 1), io.rs2(XLen - 1))
+  protected val ge         = !lt
+  protected val geu        = !ltu
   io.taken :=
     ((io.br_type === Control.BR_EQ) && eq) ||
       ((io.br_type === Control.BR_NE) && neq) ||