feat: add fence inst

Author: maksyuki

rtl/tc_l2/src/main/scala/core/inst/InstDecoderStage.scala

@@ -111,8 +111,10 @@ object InstDecoderStage {
     CSRRSI -> List(wtRegTrue, iInstType, nopAluOperNumType, csrRSIType, branchFalse, rdMemFalse, wtMemFalse, aluWtType),
     CSRRCI -> List(wtRegTrue, iInstType, nopAluOperNumType, csrRCIType, branchFalse, rdMemFalse, wtMemFalse, aluWtType),
     // system inst
-    ECALL -> List(wtRegFalse, nopInstType, nopAluOperNumType, sysECALLType, branchFalse, rdMemFalse, wtMemFalse, nopWtType),
-    MRET  -> List(wtRegFalse, nopInstType, nopAluOperNumType, sysMRETType, branchFalse, rdMemFalse, wtMemFalse, nopWtType),
+    ECALL   -> List(wtRegFalse, nopInstType, nopAluOperNumType, sysECALLType, branchFalse, rdMemFalse, wtMemFalse, nopWtType),
+    MRET    -> List(wtRegFalse, nopInstType, nopAluOperNumType, sysMRETType, branchFalse, rdMemFalse, wtMemFalse, nopWtType),
+    FENCE   -> List(wtRegFalse, nopInstType, nopAluOperNumType, aluNopType, branchFalse, rdMemFalse, wtMemFalse, nopWtType),
+    FENCE_I -> List(wtRegFalse, nopInstType, nopAluOperNumType, aluNopType, branchFalse, rdMemFalse, wtMemFalse, nopWtType),
     // custom inst
     CUST -> List(wtRegFalse, nopInstType, nopAluOperNumType, custInstType, branchFalse, rdMemFalse, wtMemFalse, nopWtType)
   )

rtl/tc_l2/src/main/scala/core/inst/InstRegexPattern.scala

@@ -101,7 +101,8 @@ object InstRegexPattern {
   def MRET       = BitPat("b00110000001000000000000001110011")
   def WFI        = BitPat("b00010000010100000000000001110011")
   def SFENCE_VMA = BitPat("b0001001??????????000000001110011")
-
+  def FENCE      = BitPat("b0000????????00000000000000001111")
+  def FENCE_I    = BitPat("b00000000000000000001000000001111")
   // custom inst such as 0x7B
   def CUST = BitPat("b0000000??????????000?????1111011")
 }