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maksyukimaksyuki
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style: modify the axi io def
1 parent 9ccc176 commit 4446534

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2 files changed

+58
-58
lines changed

2 files changed

+58
-58
lines changed

‎rtl/tc_l3/src/main/scala/core/Cache.scala‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,10 @@ class CacheIO(implicit val p: Parameters) extends Bundle {
2121

2222
class CacheModuleIO(implicit val p: Parameters) extends Bundle {
2323
val cpu = new CacheIO
24-
val nasti = new NastiIO
24+
val axi = new AxiIO
2525
}
2626

27-
trait CacheParams extends CoreParams with HasNastiParameters {
27+
trait CacheParams extends CoreParams with HasAxiParameters {
2828
val nWays = p(NWays) // Not used...
2929
val nSets = p(NSets)
3030
val bBytes = p(CacheBlockBytes)
@@ -35,7 +35,7 @@ trait CacheParams extends CoreParams with HasNastiParameters {
3535
val nWords = bBits / xlen
3636
val wBytes = xlen / 8
3737
val byteOffsetBits = log2Ceil(wBytes)
38-
val dataBeats = bBits / nastiXDataBits
38+
val dataBeats = bBits / axiXDataBits
3939
}
4040

4141
class MetaData(implicit val p: Parameters) extends Bundle with CacheParams {
@@ -61,8 +61,8 @@ class Cache(implicit val p: Parameters) extends Module with CacheParams {
6161

6262
// Counters
6363
require(dataBeats > 0)
64-
val (read_count, read_wrap_out) = Counter(io.nasti.r.fire(), dataBeats)
65-
val (write_count, write_wrap_out) = Counter(io.nasti.w.fire(), dataBeats)
64+
val (read_count, read_wrap_out) = Counter(io.axi.r.fire(), dataBeats)
65+
val (write_count, write_wrap_out) = Counter(io.axi.w.fire(), dataBeats)
6666

6767
val is_idle = state === s_IDLE
6868
val is_read = state === s_READ_CACHE
@@ -84,7 +84,7 @@ class Cache(implicit val p: Parameters) extends Module with CacheParams {
8484
val rmeta = metaMem.read(idx, ren)
8585
val rdata = Cat((dataMem.map(_.read(idx, ren).asUInt)).reverse)
8686
val rdata_buf = RegEnable(rdata, ren_reg)
87-
val refill_buf = Reg(Vec(dataBeats, UInt(nastiXDataBits.W)))
87+
val refill_buf = Reg(Vec(dataBeats, UInt(axiXDataBits.W)))
8888
val read = Mux(is_alloc_reg, refill_buf.asUInt, Mux(ren_reg, rdata, rdata_buf))
8989

9090
hit := v(idx_reg) && rmeta.tag === tag_reg // NOTE: important!!!Q
@@ -106,8 +106,8 @@ class Cache(implicit val p: Parameters) extends Module with CacheParams {
106106
val wdata = Mux(
107107
!is_alloc,
108108
Fill(nWords, cpu_data),
109-
if (refill_buf.size == 1) io.nasti.r.bits.data
110-
else Cat(io.nasti.r.bits.data, Cat(refill_buf.init.reverse))
109+
if (refill_buf.size == 1) io.axi.r.bits.data
110+
else Cat(io.axi.r.bits.data, Cat(refill_buf.init.reverse))
111111
)
112112
when(wen) {
113113
v := v.bitSet(idx_reg, true.B)
@@ -123,20 +123,20 @@ class Cache(implicit val p: Parameters) extends Module with CacheParams {
123123
}
124124
}
125125

126-
io.nasti.ar.bits := NastiReadAddressChannel(0.U, Cat(tag_reg, idx_reg) << blen.U, log2Up(nastiXDataBits / 8).U, (dataBeats - 1).U)
127-
io.nasti.ar.valid := false.B
126+
io.axi.ar.bits := AxiReadAddressChannel(0.U, Cat(tag_reg, idx_reg) << blen.U, log2Up(axiXDataBits / 8).U, (dataBeats - 1).U)
127+
io.axi.ar.valid := false.B
128128
// read data
129-
io.nasti.r.ready := state === s_REFILL
130-
when(io.nasti.r.fire()) { refill_buf(read_count) := io.nasti.r.bits.data }
129+
io.axi.r.ready := state === s_REFILL
130+
when(io.axi.r.fire()) { refill_buf(read_count) := io.axi.r.bits.data }
131131

132132
// write addr
133-
io.nasti.aw.bits := NastiWriteAddressChannel(0.U, Cat(rmeta.tag, idx_reg) << blen.U, log2Up(nastiXDataBits / 8).U, (dataBeats - 1).U)
134-
io.nasti.aw.valid := false.B
133+
io.axi.aw.bits := AxiWriteAddressChannel(0.U, Cat(rmeta.tag, idx_reg) << blen.U, log2Up(axiXDataBits / 8).U, (dataBeats - 1).U)
134+
io.axi.aw.valid := false.B
135135
// write data
136-
io.nasti.w.bits := NastiWriteDataChannel(Vec.tabulate(dataBeats)(i => read((i + 1) * nastiXDataBits - 1, i * nastiXDataBits))(write_count), None, write_wrap_out)
137-
io.nasti.w.valid := false.B
136+
io.axi.w.bits := AxiWriteDataChannel(Vec.tabulate(dataBeats)(i => read((i + 1) * axiXDataBits - 1, i * axiXDataBits))(write_count), None, write_wrap_out)
137+
io.axi.w.valid := false.B
138138
// write resp
139-
io.nasti.b.ready := false.B
139+
io.axi.b.ready := false.B
140140

141141
// Cache FSM
142142
val is_dirty = v(idx_reg) && d(idx_reg)
@@ -154,11 +154,11 @@ class Cache(implicit val p: Parameters) extends Module with CacheParams {
154154
state := s_IDLE
155155
}
156156
}.otherwise {
157-
io.nasti.aw.valid := is_dirty
158-
io.nasti.ar.valid := !is_dirty
159-
when(io.nasti.aw.fire()) {
157+
io.axi.aw.valid := is_dirty
158+
io.axi.ar.valid := !is_dirty
159+
when(io.axi.aw.fire()) {
160160
state := s_WRITE_BACK
161-
}.elsewhen(io.nasti.ar.fire()) {
161+
}.elsewhen(io.axi.ar.fire()) {
162162
state := s_REFILL
163163
}
164164
}
@@ -167,30 +167,30 @@ class Cache(implicit val p: Parameters) extends Module with CacheParams {
167167
when(hit || is_alloc_reg || io.cpu.abort) {
168168
state := s_IDLE
169169
}.otherwise {
170-
io.nasti.aw.valid := is_dirty
171-
io.nasti.ar.valid := !is_dirty
172-
when(io.nasti.aw.fire()) {
170+
io.axi.aw.valid := is_dirty
171+
io.axi.ar.valid := !is_dirty
172+
when(io.axi.aw.fire()) {
173173
state := s_WRITE_BACK
174-
}.elsewhen(io.nasti.ar.fire()) {
174+
}.elsewhen(io.axi.ar.fire()) {
175175
state := s_REFILL
176176
}
177177
}
178178
}
179179
is(s_WRITE_BACK) {
180-
io.nasti.w.valid := true.B
180+
io.axi.w.valid := true.B
181181
when(write_wrap_out) {
182182
state := s_WRITE_ACK
183183
}
184184
}
185185
is(s_WRITE_ACK) {
186-
io.nasti.b.ready := true.B
187-
when(io.nasti.b.fire()) {
186+
io.axi.b.ready := true.B
187+
when(io.axi.b.fire()) {
188188
state := s_REFILL_READY
189189
}
190190
}
191191
is(s_REFILL_READY) {
192-
io.nasti.ar.valid := true.B
193-
when(io.nasti.ar.fire()) {
192+
io.axi.ar.valid := true.B
193+
when(io.axi.ar.fire()) {
194194
state := s_REFILL
195195
}
196196
}

‎rtl/tc_l3/src/main/scala/core/Processor.scala‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,9 @@ import chisel._
44
import chisel.uitl._
55

66
class MemArbiterIO(implicit val p: Parameters) extends Bundle {
7-
val icache = Flipped(new NastiIO)
8-
val dcache = Flipped(new NastiIO)
9-
val nasti = new NastiIO
7+
val icache = Flipped(new AxiIO)
8+
val dcache = Flipped(new AxiIO)
9+
val axi = new AxiIO
1010
}
1111

1212
class MemArbiter(implicit p: Parameters) extends Module {
@@ -16,41 +16,41 @@ class MemArbiter(implicit p: Parameters) extends Module {
1616
val state = RegInit(s_IDLE)
1717

1818
// write address
19-
io.nasti.aw.bits := io.dcache.aw.bits
20-
io.nasti.aw.valid := io.dcache.aw.valid && state === s_IDLE
21-
io.dcache.aw.ready := io.nasti.aw.ready && state === s_IDLE
19+
io.axi.aw.bits := io.dcache.aw.bits
20+
io.axi.aw.valid := io.dcache.aw.valid && state === s_IDLE
21+
io.dcache.aw.ready := io.axi.aw.ready && state === s_IDLE
2222
io.icache.aw := DontCare
2323

2424
// write data
25-
io.nasti.w.bits := io.dcache.w.bits
26-
io.nasti.w.valid := io.dcache.w.valid && state === s_DCACHE_WRITE
27-
io.dcache.w.ready := io.nasti.w.ready && state === s_DCACHE_WRITE
25+
io.axi.w.bits := io.dcache.w.bits
26+
io.axi.w.valid := io.dcache.w.valid && state === s_DCACHE_WRITE
27+
io.dcache.w.ready := io.axi.w.ready && state === s_DCACHE_WRITE
2828
io.icache.w := DontCare
2929

3030
// write ack
31-
io.dcache.b.bits := io.nasti.b.bits
32-
io.dcache.b.valid := io.nasti.b.valid && state === s_DCACHE_ACK
33-
io.nasti.b.ready := io.dcache.b.ready && state === s_DCACHE_ACK
31+
io.dcache.b.bits := io.axi.b.bits
32+
io.dcache.b.valid := io.axi.b.valid && state === s_DCACHE_ACK
33+
io.axi.b.ready := io.dcache.b.ready && state === s_DCACHE_ACK
3434
io.icache.b := DontCare
3535

3636
// Read Address
37-
io.nasti.ar.bits := NastiReadAddressChannel(
37+
io.axi.ar.bits := AxiReadAddressChannel(
3838
Mux(io.dcache.ar.valid, io.dcache.ar.bits.id, io.icache.ar.bits.id),
3939
Mux(io.dcache.ar.valid, io.dcache.ar.bits.addr, io.icache.ar.bits.addr),
4040
Mux(io.dcache.ar.valid, io.dcache.ar.bits.size, io.icache.ar.bits.size),
4141
Mux(io.dcache.ar.valid, io.dcache.ar.bits.len, io.icache.ar.bits.len)
4242
)
43-
io.nasti.ar.valid := (io.icache.ar.valid || io.dcache.ar.valid) &&
44-
!io.nasti.aw.valid && state === s_IDLE
45-
io.dcache.ar.ready := io.nasti.ar.ready && !io.nasti.aw.valid && state === s_IDLE
43+
io.axi.ar.valid := (io.icache.ar.valid || io.dcache.ar.valid) &&
44+
!io.axi.aw.valid && state === s_IDLE
45+
io.dcache.ar.ready := io.axi.ar.ready && !io.axi.aw.valid && state === s_IDLE
4646
io.icache.ar.ready := io.dcache.ar.ready && !io.dcache.ar.valid
4747

4848
// Read Data
49-
io.icache.r.bits := io.nasti.r.bits
50-
io.dcache.r.bits := io.nasti.r.bits
51-
io.icache.r.valid := io.nasti.r.valid && state === s_ICACHE_READ
52-
io.dcache.r.valid := io.nasti.r.valid && state === s_DCACHE_READ
53-
io.nasti.r.ready := io.icache.r.ready && state === s_ICACHE_READ ||
49+
io.icache.r.bits := io.axi.r.bits
50+
io.dcache.r.bits := io.axi.r.bits
51+
io.icache.r.valid := io.axi.r.valid && state === s_ICACHE_READ
52+
io.dcache.r.valid := io.axi.r.valid && state === s_DCACHE_READ
53+
io.axi.r.ready := io.icache.r.ready && state === s_ICACHE_READ ||
5454
io.dcache.r.ready && state === s_DCACHE_READ
5555

5656
switch(state) {
@@ -64,12 +64,12 @@ class MemArbiter(implicit p: Parameters) extends Module {
6464
}
6565
}
6666
is(s_ICACHE_READ) {
67-
when(io.nasti.r.fire() && io.nasti.r.bits.last) {
67+
when(io.axi.r.fire() && io.axi.r.bits.last) {
6868
state := s_IDLE
6969
}
7070
}
7171
is(s_DCACHE_READ) {
72-
when(io.nasti.r.fire() && io.nasti.r.bits.last) {
72+
when(io.axi.r.fire() && io.axi.r.bits.last) {
7373
state := s_IDLE
7474
}
7575
}
@@ -79,7 +79,7 @@ class MemArbiter(implicit p: Parameters) extends Module {
7979
}
8080
}
8181
is(s_DCACHE_ACK) {
82-
when(io.nasti.b.fire()) {
82+
when(io.axi.b.fire()) {
8383
state := s_IDLE
8484
}
8585
}
@@ -88,7 +88,7 @@ class MemArbiter(implicit p: Parameters) extends Module {
8888

8989
class ProcessorIO(implicit val p: Parameters) extends Bundle {
9090
val host = new HostIO
91-
val nasti = new NastiIO
91+
val axi = new AxiIO
9292
}
9393

9494
class Processor(implicit p: Parameters) extends Module {
@@ -101,7 +101,7 @@ class Processor(implicit p: Parameters) extends Module {
101101
io.host <> core.io.host
102102
core.io.icache <> icache.io.cpu
103103
core.io.dcache <> dcache.io.cpu
104-
arb.io.icache <> icache.io.nasti
105-
arb.io.dcache <> dcache.io.nasti
106-
io.nasti <> arb.io.nasti
104+
arb.io.icache <> icache.io.axi
105+
arb.io.dcache <> dcache.io.axi
106+
io.axi <> arb.io.axi
107107
}

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