refactor: move bpu const var to instconfig

Author: maksyuki

rtl/tc_l2/src/main/scala/common/ConstVal.scala

@@ -27,12 +27,4 @@ object ConstVal {
   val MSipOffset     = 0x0.U(CLINTAddrLen.W)
   val MTimeOffset    = 0xbff8.U(CLINTAddrLen.W)
   val MTimeCmpOffset = 0x4000.U(CLINTAddrLen.W)
-
-  // branch prediction
-  val GHRLen    = 5
-  val PHTSize   = 1 << GHRLen
-  val BTBIdxLen = 5
-  val BTBPcLen  = AddrLen - BTBIdxLen
-  val BTBTgtLen = AddrLen
-  val BTBSize   = 1 << BTBIdxLen
 }

rtl/tc_l2/src/main/scala/common/InstConfig.scala

@@ -95,6 +95,14 @@ trait InstConfig {
   val instFENCE_I = 59.U(InstValLen.W)
   val instCUST    = 60.U(InstValLen.W)
 
+  // branch prediction
+  val GHRLen    = 5
+  val PHTSize   = 1 << GHRLen
+  val BTBIdxLen = 5
+  val BTBPcLen  = XLen - BTBIdxLen
+  val BTBTgtLen = XLen
+  val BTBSize   = 1 << BTBIdxLen
+
   // cache
   val NWay          = 4
   val NBank         = 4

rtl/tc_l2/src/main/scala/core/exec/BEU.scala

@@ -3,7 +3,7 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.{ConstVal, InstConfig}
+import treecorel2.common.InstConfig
 
 class BEU extends Module with InstConfig {
   val io = IO(new Bundle {
@@ -12,7 +12,7 @@ class BEU extends Module with InstConfig {
     val src1       = Input(UInt(XLen.W))
     val src2       = Input(UInt(XLen.W))
     val pc         = Input(UInt(XLen.W))
-    val branIdx    = Input(UInt(ConstVal.GHRLen.W))
+    val branIdx    = Input(UInt(GHRLen.W))
     val branchInfo = new BRANCHIO
     val branch     = Output(Bool())
     val tgt        = Output(UInt(XLen.W))

rtl/tc_l2/src/main/scala/core/if/BPU.scala

@@ -3,9 +3,9 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.ConstVal
+import treecorel2.common.{ConstVal, InstConfig}
 
-class BPU extends Module {
+class BPU extends Module with InstConfig {
   // 2BP 2BC
   // Two-level adaptive predictor
   val io = IO(new Bundle {
@@ -14,7 +14,7 @@ class BPU extends Module {
     val lookupPc  = Input(UInt(ConstVal.AddrLen.W))
     val predTaken = Output(Bool())
     val predTgt   = Output(UInt(ConstVal.AddrLen.W))
-    val predIdx   = Output(UInt(ConstVal.GHRLen.W))
+    val predIdx   = Output(UInt(GHRLen.W))
   })
 
   protected val ghr = Module(new GHR)
@@ -25,7 +25,7 @@ class BPU extends Module {
   ghr.io.taken  := io.branchInfo.taken
 
   // G-share
-  protected val idx = io.lookupPc(ConstVal.GHRLen - 1, 0) ^ ghr.io.idx
+  protected val idx = io.lookupPc(GHRLen - 1, 0) ^ ghr.io.idx
   pht.io.prevBranch := io.branchInfo.branch
   pht.io.prevTaken  := io.branchInfo.taken
   pht.io.prevIdx    := io.branchInfo.idx

rtl/tc_l2/src/main/scala/core/if/BTB.scala

@@ -3,15 +3,15 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.ConstVal
+import treecorel2.common.{ConstVal, InstConfig}
 
 class BTBLine extends Bundle {
   val pc   = UInt(ConstVal.AddrLen.W)
   val tgt  = UInt(ConstVal.AddrLen.W)
   val jump = Bool()
 }
 
-class BTB extends Module {
+class BTB extends Module with InstConfig {
   val io = IO(new Bundle {
     // branch info (from idu)
     val branch = Input(Bool())
@@ -26,11 +26,11 @@ class BTB extends Module {
   })
 
   // definitions of BTB lines and valid bits
-  protected val valids = RegInit(VecInit(Seq.fill(ConstVal.BTBSize) { false.B }))
-  protected val lines  = Mem(ConstVal.BTBSize, new BTBLine)
+  protected val valids = RegInit(VecInit(Seq.fill(BTBSize) { false.B }))
+  protected val lines  = Mem(BTBSize, new BTBLine)
 
   // branch info for BTB lines
-  protected val idx = io.pc(ConstVal.BTBIdxLen - 1, 0)
+  protected val idx = io.pc(BTBIdxLen - 1, 0)
   // write to BTB lines
   when(io.branch) {
     valids(idx)     := true.B
@@ -40,7 +40,7 @@ class BTB extends Module {
   }
 
   // signals about BTB lookup
-  protected val lookupIdx   = io.lookupPc(ConstVal.BTBIdxLen - 1, 0)
+  protected val lookupIdx   = io.lookupPc(BTBIdxLen - 1, 0)
   protected val lookupPcSel = io.lookupPc
   protected val btbHit      = valids(lookupIdx) && lines(lookupIdx).pc === lookupPcSel
 

rtl/tc_l2/src/main/scala/core/if/GHR.scala

@@ -3,19 +3,19 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.ConstVal
+import treecorel2.common.{ConstVal, InstConfig}
 
-class GHR extends Module {
+class GHR extends Module with InstConfig {
   val io = IO(new Bundle {
     val branch = Input(Bool())
     val taken  = Input(Bool())
-    val idx    = Output(UInt(ConstVal.GHRLen.W))
+    val idx    = Output(UInt(GHRLen.W))
   })
 
-  protected val shiftReg = Reg(UInt(ConstVal.GHRLen.W))
+  protected val shiftReg = Reg(UInt(GHRLen.W))
 
   when(io.branch) {
-    shiftReg := Cat(shiftReg(ConstVal.GHRLen - 2, 0), io.taken)
+    shiftReg := Cat(shiftReg(GHRLen - 2, 0), io.taken)
   }
 
   io.idx := shiftReg

rtl/tc_l2/src/main/scala/core/if/PHT.scala

@@ -3,21 +3,21 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.ConstVal
+import treecorel2.common.InstConfig
 
-class PHT extends Module {
+class PHT extends Module with InstConfig {
   val io = IO(new Bundle {
     // branch info (from idu)
     val prevBranch = Input(Bool())
     val prevTaken  = Input(Bool())
-    val prevIdx    = Input(UInt(ConstVal.GHRLen.W))
+    val prevIdx    = Input(UInt(GHRLen.W))
     // index for looking up counter table
-    val idx = Input(UInt(ConstVal.GHRLen.W))
+    val idx = Input(UInt(GHRLen.W))
     // prediction result
     val taken = Output(Bool())
   })
 
-  protected val init     = Seq.fill(ConstVal.PHTSize) { "b10".U(2.W) }
+  protected val init     = Seq.fill(PHTSize) { "b10".U(2.W) }
   protected val counters = RegInit(VecInit(init))
 
   // update counter

rtl/tc_l2/src/main/scala/port/BRANCH.scala

@@ -3,13 +3,13 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.ConstVal
+import treecorel2.common.{ConstVal, InstConfig}
 
 class BRANCHIO extends Bundle {
   val branch = Output(Bool()) // prev inst is a b/j
   val jump   = Output(Bool()) // is 'jal' or 'jalr'
   val taken  = Output(Bool()) // is prev branch taken
-  val idx    = Output(UInt(ConstVal.GHRLen.W)) // prev idx of PHT
+  val idx    = Output(UInt(5.W)) // prev idx of PHT(GHRLen)
   val pc     = Output(UInt(ConstVal.AddrLen.W)) // prev instruction PC
   val tgt    = Output(UInt(ConstVal.AddrLen.W)) // prev branch tgt
 }

rtl/tc_l2/src/main/scala/port/IF2IDIO.scala

@@ -3,12 +3,12 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.ConstVal
+import treecorel2.common.InstConfig
 
 class IF2IDIO extends Bundle {
   val valid     = Output(Bool())
   val inst      = Output(UInt(32.W))
   val pc        = Output(UInt(64.W))
-  val branIdx   = Output(UInt(ConstVal.GHRLen.W))
+  val branIdx   = Output(UInt(5.W)) // (GHRLen)
   val predTaken = Output(Bool())
 }