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1 parent 48fbe32 commit 65044d3Copy full SHA for 65044d3
rtl/tc_l3/src/main/scala/core/Core.scala
@@ -3,7 +3,23 @@ package treecorel3
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import chisel._
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import chisel.uitl._
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+class HostIO(implicit p: Parameters) extends Bundle {
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+ val fromhost = Flipped(Valid(UInt(xlen.W)))
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+ val tohost = Output(UInt(xlen.W))
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+}
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+
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+class CoreIO(implicit p: Parameters) extends Bundle {
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+ val host = new HostIO
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+ val icache = Flipped((new CacheIO))
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+ val dcache = Flipped((new CacheIO))
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class Core(implicit val p: Parameters) extends Module {
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+ val io = IO(new CoreIO)
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val dpath = Module(new DataPath)
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val ctrl = Module(new Control)
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+ io.icache <> dpath.io.icache
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+ io.dcache <> dpath.io.dcache
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+ ctrl.io <> dpath.io.ctrl
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}
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