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maksyukimaksyuki
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style: format the code of some modules
1 parent a60c70d commit 797c5a3

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6 files changed

+63
-65
lines changed

6 files changed

+63
-65
lines changed

‎rtl/tc_l3/src/main/scala/core/CSR.scala‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -227,13 +227,13 @@ class CSR(implicit val p: Parameters) extends Module {
227227
io.out := Lookup(csr_addr, 0.U, csrFile).asUInt
228228

229229
val privValid = csr_addr(9, 8) <= PRV
230-
val privInst = io.cmd === CSR.P
231-
val isEcall = privInst && !csr_addr(0) && !csr_addr(8)
232-
val isEbreak = privInst && csr_addr(0) && !csr_addr(8)
233-
val isEret = privInst && !csr_addr(0) && csr_addr(8)
230+
val privInst = io.cmd === CSR.P
231+
val isEcall = privInst && !csr_addr(0) && !csr_addr(8)
232+
val isEbreak = privInst && csr_addr(0) && !csr_addr(8)
233+
val isEret = privInst && !csr_addr(0) && csr_addr(8)
234234
val csrValid = csrFile.map(_._1 === csr_addr).reduce(_ || _)
235-
val csrRO = csr_addr(11, 10).andR || csr_addr === CSR.mtvec || csr_addr === CSR.mtdeleg
236-
val wen = io.cmd === CSR.W || io.cmd(1) && rs1_addr.orR
235+
val csrRO = csr_addr(11, 10).andR || csr_addr === CSR.mtvec || csr_addr === CSR.mtdeleg
236+
val wen = io.cmd === CSR.W || io.cmd(1) && rs1_addr.orR
237237
val wdata = MuxLookup(
238238
io.cmd,
239239
0.U,
@@ -264,10 +264,10 @@ class CSR(implicit val p: Parameters) extends Module {
264264
)
265265

266266
io.expt := io.illegal || iaddrInvalid || laddrInvalid || saddrInvalid ||
267-
io.cmd(1, 0).orR && (!csrValid || !privValid) || wen && csrRO ||
268-
(privInst && !privValid) || isEcall || isEbreak
269-
io.evec := mtvec + (PRV << 6)
270-
io.epc := mepc
267+
io.cmd(1, 0).orR && (!csrValid || !privValid) || wen && csrRO ||
268+
(privInst && !privValid) || isEcall || isEbreak
269+
io.evec := mtvec + (PRV << 6)
270+
io.epc := mepc
271271

272272
// Counters
273273
time := time + 1.U

‎rtl/tc_l3/src/main/scala/core/Cache.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ class CacheIO(implicit val p: Parameters) extends Bundle {
2121

2222
class CacheModuleIO(implicit val p: Parameters) extends Bundle {
2323
val cpu = new CacheIO
24-
val axi = new AxiIO
24+
val axi = new AXI4IO
2525
}
2626

2727
trait CacheParams extends CoreParams with HasAxiParameters {
@@ -71,8 +71,8 @@ class Cache(implicit val p: Parameters) extends Module with CacheParams {
7171
val is_alloc_reg = RegNext(is_alloc)
7272

7373
val hit = Wire(Bool())
74-
val wen = is_write && (hit || is_alloc_reg) && !io.cpu.abort || is_alloc
75-
val ren = !wen && (is_idle || is_read) && io.cpu.req.valid
74+
val wen = is_write && (hit || is_alloc_reg) && !io.cpu.abort || is_alloc
75+
val ren = !wen && (is_idle || is_read) && io.cpu.req.valid
7676
val ren_reg = RegNext(ren)
7777

7878
val addr = io.cpu.req.bits.addr

‎rtl/tc_l3/src/main/scala/core/Processor.scala‎

Lines changed: 41 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -3,100 +3,96 @@ package treecorel3
33
import chisel._
44
import chisel.uitl._
55

6-
class MemArbiterIO(implicit val p: Parameters) extends Bundle {
7-
val icache = Flipped(new AxiIO)
8-
val dcache = Flipped(new AxiIO)
9-
val axi = new AxiIO
6+
class MemArbiterIO extends Bundle {
7+
val icache = Flipped(new AXI4IO)
8+
val dcache = Flipped(new AXI4IO)
9+
val axi = new AXI4IO
1010
}
1111

12-
class MemArbiter(implicit p: Parameters) extends Module {
12+
class MemArbiter extends Module {
1313
val io = IO(new MemArbiterIO)
1414

15-
val s_IDLE :: s_ICACHE_READ :: s_DCACHE_READ :: s_DCACHE_WRITE :: s_DCACHE_ACK :: Nil = Enum(5)
16-
val state = RegInit(s_IDLE)
15+
val eumIDLE :: eumICacheRd :: eumDCacheRd :: eumDCacheWt :: eumDCacheAck :: Nil = Enum(5)
16+
17+
protected val state = RegInit(eumIDLE)
1718

18-
// write address
1919
io.axi.aw.bits := io.dcache.aw.bits
20-
io.axi.aw.valid := io.dcache.aw.valid && state === s_IDLE
21-
io.dcache.aw.ready := io.axi.aw.ready && state === s_IDLE
20+
io.axi.aw.valid := io.dcache.aw.valid && state === eumIDLE
21+
io.dcache.aw.ready := io.axi.aw.ready && state === eumIDLE
2222
io.icache.aw := DontCare
2323

24-
// write data
2524
io.axi.w.bits := io.dcache.w.bits
26-
io.axi.w.valid := io.dcache.w.valid && state === s_DCACHE_WRITE
27-
io.dcache.w.ready := io.axi.w.ready && state === s_DCACHE_WRITE
25+
io.axi.w.valid := io.dcache.w.valid && state === eumDCacheWt
26+
io.dcache.w.ready := io.axi.w.ready && state === eumDCacheWt
2827
io.icache.w := DontCare
2928

30-
// write ack
3129
io.dcache.b.bits := io.axi.b.bits
32-
io.dcache.b.valid := io.axi.b.valid && state === s_DCACHE_ACK
33-
io.axi.b.ready := io.dcache.b.ready && state === s_DCACHE_ACK
30+
io.dcache.b.valid := io.axi.b.valid && state === eumDCacheAck
31+
io.axi.b.ready := io.dcache.b.ready && state === eumDCacheAck
3432
io.icache.b := DontCare
3533

36-
// Read Address
3734
io.axi.ar.bits := AxiReadAddressChannel(
3835
Mux(io.dcache.ar.valid, io.dcache.ar.bits.id, io.icache.ar.bits.id),
3936
Mux(io.dcache.ar.valid, io.dcache.ar.bits.addr, io.icache.ar.bits.addr),
4037
Mux(io.dcache.ar.valid, io.dcache.ar.bits.size, io.icache.ar.bits.size),
4138
Mux(io.dcache.ar.valid, io.dcache.ar.bits.len, io.icache.ar.bits.len)
4239
)
43-
io.axi.ar.valid := (io.icache.ar.valid || io.dcache.ar.valid) &&
44-
!io.axi.aw.valid && state === s_IDLE
45-
io.dcache.ar.ready := io.axi.ar.ready && !io.axi.aw.valid && state === s_IDLE
46-
io.icache.ar.ready := io.dcache.ar.ready && !io.dcache.ar.valid
40+
io.axi.ar.valid := (io.icache.ar.valid || io.dcache.ar.valid) && !io.axi.aw.valid && state === eumIDLE
41+
io.dcache.ar.ready := io.axi.ar.ready && !io.axi.aw.valid && state === eumIDLE
42+
io.icache.ar.ready := io.dcache.ar.ready && !io.dcache.ar.valid
4743

4844
// Read Data
4945
io.icache.r.bits := io.axi.r.bits
5046
io.dcache.r.bits := io.axi.r.bits
51-
io.icache.r.valid := io.axi.r.valid && state === s_ICACHE_READ
52-
io.dcache.r.valid := io.axi.r.valid && state === s_DCACHE_READ
53-
io.axi.r.ready := io.icache.r.ready && state === s_ICACHE_READ ||
54-
io.dcache.r.ready && state === s_DCACHE_READ
47+
io.icache.r.valid := io.axi.r.valid && state === eumICacheRd
48+
io.dcache.r.valid := io.axi.r.valid && state === eumDCacheRd
49+
io.axi.r.ready := io.icache.r.ready && state === eumICacheRd ||
50+
io.dcache.r.ready && state === eumDCacheRd
5551

5652
switch(state) {
57-
is(s_IDLE) {
53+
is(eumIDLE) {
5854
when(io.dcache.aw.fire()) {
59-
state := s_DCACHE_WRITE
55+
state := eumDCacheWt
6056
}.elsewhen(io.dcache.ar.fire()) {
61-
state := s_DCACHE_READ
57+
state := eumDCacheRd
6258
}.elsewhen(io.icache.ar.fire()) {
63-
state := s_ICACHE_READ
59+
state := eumICacheRd
6460
}
6561
}
66-
is(s_ICACHE_READ) {
62+
is(eumICacheRd) {
6763
when(io.axi.r.fire() && io.axi.r.bits.last) {
68-
state := s_IDLE
64+
state := eumIDLE
6965
}
7066
}
71-
is(s_DCACHE_READ) {
67+
is(eumDCacheRd) {
7268
when(io.axi.r.fire() && io.axi.r.bits.last) {
73-
state := s_IDLE
69+
state := eumIDLE
7470
}
7571
}
76-
is(s_DCACHE_WRITE) {
72+
is(eumDCacheWt) {
7773
when(io.dcache.w.fire() && io.dcache.w.bits.last) {
78-
state := s_DCACHE_ACK
74+
state := eumDCacheAck
7975
}
8076
}
81-
is(s_DCACHE_ACK) {
77+
is(eumDCacheAck) {
8278
when(io.axi.b.fire()) {
83-
state := s_IDLE
79+
state := eumIDLE
8480
}
8581
}
8682
}
8783
}
8884

89-
class ProcessorIO(implicit val p: Parameters) extends Bundle {
85+
class ProcessorIO extends Bundle {
9086
val host = new HostIO
91-
val axi = new AxiIO
87+
val axi = new AXI4IO
9288
}
9389

94-
class Processor(implicit p: Parameters) extends Module {
95-
val io = IO(new ProcessorIO)
96-
val core = Module(new Core)
97-
val icache = Module(new Cache)
98-
val dcache = Module(new Cache)
99-
val arb = Module(new MemArbiter)
90+
class Processor extends Module {
91+
val io = IO(new ProcessorIO)
92+
protected val core = Module(new Core)
93+
protected val icache = Module(new Cache)
94+
protected val dcache = Module(new Cache)
95+
protected val arb = Module(new MemArbiter)
10096

10197
io.host <> core.io.host
10298
core.io.icache <> icache.io.cpu

‎rtl/tc_l3/src/main/scala/core/ex/BrCond.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,10 @@ class BrCond(implicit val p: Parameters) extends Module {
2121
val ge = !lt
2222
val geu = !ltu
2323
io.taken :=
24-
((io.br_type === Control.BR_EQ) && eq) ||
25-
((io.br_type === Control.BR_NE) && neq) ||
26-
((io.br_type === Control.BR_LT) && lt) ||
27-
((io.br_type === Control.BR_GE) && ge) ||
24+
((io.br_type === Control.BR_EQ) && eq) ||
25+
((io.br_type === Control.BR_NE) && neq) ||
26+
((io.br_type === Control.BR_LT) && lt) ||
27+
((io.br_type === Control.BR_GE) && ge) ||
2828
((io.br_type === Control.BR_LTU) && ltu) ||
2929
((io.br_type === Control.BR_GEU) && geu)
3030
}

‎rtl/tc_l3/src/main/scala/top/SimTop.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ class SimTop extends Module {
1111
val logCtrl = new LogCtrlIO
1212
val perfInfo = new PerfInfoIO
1313
val uart = new UARTIO
14-
val memAXI_0 = new AxiIO
14+
val memAXI_0 = new AXI4IO
1515
})
1616

1717
protected val proc = Module(new Processor)

‎rtl/tc_l3/src/main/scala/top/TopMain.scala‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,10 @@ package top
22

33
import sim._
44

5-
object TopMain extends App {
6-
if (true) {
5+
import treecorel3.InstConfig
6+
7+
object TopMain extends App with InstConfig {
8+
if (!SoCEna) {
79
(new chisel3.stage.ChiselStage).execute(
810
args,
911
Seq(

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