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maksyukimaksyuki
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refactor:modify imm decoder impl
1 parent 3a38371 commit 7b8a2cf

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8 files changed

+217
-118
lines changed

8 files changed

+217
-118
lines changed

‎rtl/tc_l2/src/main/scala/common/InstConfig.scala‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,17 @@ trait InstConfig {
1919
val DiffRWSize = 3.U
2020
val CacheEna = false
2121

22+
// inst type
23+
// nop is equal to [addi x0, x0, 0], so the oper is same as 'addi' inst
24+
val InstTypeLen = 3
25+
val nopInstType = 2.U(InstTypeLen.W)
26+
val rInstType = 1.U(InstTypeLen.W)
27+
val iInstType = 2.U(InstTypeLen.W)
28+
val sInstType = 3.U(InstTypeLen.W)
29+
val bInstType = 4.U(InstTypeLen.W)
30+
val uInstType = 5.U(InstTypeLen.W)
31+
val jInstType = 6.U(InstTypeLen.W)
32+
2233
val NWay = 4
2334
val NBank = 4
2435
val NSet = 32

‎rtl/tc_l2/src/main/scala/core/exec/ALU.scala‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,45 +8,45 @@ class ALU extends Module {
88
val isa = Input(new ISAIO)
99
val src1 = Input(UInt(64.W))
1010
val src2 = Input(UInt(64.W))
11-
val imm = Input(new IMMIO)
11+
val imm = Input(UInt(64.W))
1212
val res = Output(UInt(64.W))
1313
})
1414

15-
protected val addi = SignExt(io.isa.ADDI.asUInt, 64) & (io.src1 + io.imm.I)
15+
protected val addi = SignExt(io.isa.ADDI.asUInt, 64) & (io.src1 + io.imm)
1616
protected val add = SignExt(io.isa.ADD.asUInt, 64) & (io.src1 + io.src2)
17-
protected val lui = SignExt(io.isa.LUI.asUInt, 64) & (io.imm.U)
17+
protected val lui = SignExt(io.isa.LUI.asUInt, 64) & (io.imm)
1818
protected val sub = SignExt(io.isa.SUB.asUInt, 64) & (io.src1 - io.src2)
19-
protected val addiw = SignExt(io.isa.ADDIW.asUInt, 64) & SignExt((io.src1 + io.imm.I)(31, 0), 64)
19+
protected val addiw = SignExt(io.isa.ADDIW.asUInt, 64) & SignExt((io.src1 + io.imm)(31, 0), 64)
2020
protected val addw = SignExt(io.isa.ADDW.asUInt, 64) & SignExt((io.src1 + io.src2)(31, 0), 64)
2121
protected val subw = SignExt(io.isa.SUBW.asUInt, 64) & SignExt((io.src1 - io.src2)(31, 0), 64)
2222
protected val arith = addi | add | lui | sub | addiw | addw | subw
2323

24-
protected val andi = SignExt(io.isa.ANDI.asUInt, 64) & (io.src1 & io.imm.I)
24+
protected val andi = SignExt(io.isa.ANDI.asUInt, 64) & (io.src1 & io.imm)
2525
protected val and = SignExt(io.isa.AND.asUInt, 64) & (io.src1 & io.src2)
26-
protected val ori = SignExt(io.isa.ORI.asUInt, 64) & (io.src1 | io.imm.I)
26+
protected val ori = SignExt(io.isa.ORI.asUInt, 64) & (io.src1 | io.imm)
2727
protected val or = SignExt(io.isa.OR.asUInt, 64) & (io.src1 | io.src2)
28-
protected val xori = SignExt(io.isa.XORI.asUInt, 64) & (io.src1 ^ io.imm.I)
28+
protected val xori = SignExt(io.isa.XORI.asUInt, 64) & (io.src1 ^ io.imm)
2929
protected val xor = SignExt(io.isa.XOR.asUInt, 64) & (io.src1 ^ io.src2)
3030
protected val logc = andi | and | ori | or | xori | xor
3131

3232
protected val slt = Mux((io.isa.SLT && (io.src1.asSInt < io.src2.asSInt)), 1.U(64.W), 0.U(64.W))
33-
protected val slti = Mux((io.isa.SLTI && (io.src1.asSInt < io.imm.I.asSInt)), 1.U(64.W), 0.U(64.W))
33+
protected val slti = Mux((io.isa.SLTI && (io.src1.asSInt < io.imm.asSInt)), 1.U(64.W), 0.U(64.W))
3434
protected val sltu = Mux((io.isa.SLTU && (io.src1.asUInt < io.src2.asUInt)), 1.U(64.W), 0.U(64.W))
35-
protected val sltiu = Mux((io.isa.SLTIU && (io.src1.asUInt < io.imm.I.asUInt)), 1.U(64.W), 0.U(64.W))
35+
protected val sltiu = Mux((io.isa.SLTIU && (io.src1.asUInt < io.imm.asUInt)), 1.U(64.W), 0.U(64.W))
3636
protected val comp = slt | slti | sltu | sltiu
3737

3838
protected val sll = SignExt(io.isa.SLL.asUInt, 64) & (io.src1 << io.src2(5, 0))(63, 0)
3939
protected val srl = SignExt(io.isa.SRL.asUInt, 64) & (io.src1 >> io.src2(5, 0))
4040
protected val sra = SignExt(io.isa.SRA.asUInt, 64) & (io.src1.asSInt >> io.src2(5, 0)).asUInt
41-
protected val slli = SignExt(io.isa.SLLI.asUInt, 64) & (io.src1 << io.imm.I(5, 0))(63, 0)
42-
protected val srli = SignExt(io.isa.SRLI.asUInt, 64) & (io.src1 >> io.imm.I(5, 0))
43-
protected val srai = SignExt(io.isa.SRAI.asUInt, 64) & (io.src1.asSInt >> io.imm.I(5, 0)).asUInt
41+
protected val slli = SignExt(io.isa.SLLI.asUInt, 64) & (io.src1 << io.imm(5, 0))(63, 0)
42+
protected val srli = SignExt(io.isa.SRLI.asUInt, 64) & (io.src1 >> io.imm(5, 0))
43+
protected val srai = SignExt(io.isa.SRAI.asUInt, 64) & (io.src1.asSInt >> io.imm(5, 0)).asUInt
4444
protected val sllw = SignExt(io.isa.SLLW.asUInt, 64) & SignExt((io.src1 << io.src2(4, 0))(31, 0), 64)
4545
protected val srlw = SignExt(io.isa.SRLW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.src2(4, 0)), 64)
4646
protected val sraw = SignExt(io.isa.SRAW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.src2(4, 0)).asUInt, 64)
47-
protected val slliw = SignExt(io.isa.SLLIW.asUInt, 64) & SignExt((io.src1 << io.imm.I(4, 0))(31, 0), 64)
48-
protected val srliw = SignExt(io.isa.SRLIW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.imm.I(4, 0)), 64)
49-
protected val sraiw = SignExt(io.isa.SRAIW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.imm.I(4, 0)).asUInt, 64)
47+
protected val slliw = SignExt(io.isa.SLLIW.asUInt, 64) & SignExt((io.src1 << io.imm(4, 0))(31, 0), 64)
48+
protected val srliw = SignExt(io.isa.SRLIW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.imm(4, 0)), 64)
49+
protected val sraiw = SignExt(io.isa.SRAIW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.imm(4, 0)).asUInt, 64)
5050
protected val shift = sll | srl | sra | slli | srli | srai | sllw | srlw | sraw | slliw | srliw | sraiw
5151

5252
io.res := arith | logc | comp | shift

‎rtl/tc_l2/src/main/scala/core/exec/BEU.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ import treecorel2.common.{ConstVal, InstConfig}
88
class BEU extends Module with InstConfig {
99
val io = IO(new Bundle {
1010
val isa = Input(new ISAIO)
11-
val imm = Input(new IMMIO)
11+
val imm = Input(UInt(XLen.W))
1212
val src1 = Input(UInt(XLen.W))
1313
val src2 = Input(UInt(XLen.W))
1414
val pc = Input(UInt(XLen.W))
@@ -30,9 +30,9 @@ class BEU extends Module with InstConfig {
3030
protected val jal = io.isa.JAL
3131
protected val jalr = io.isa.JALR
3232

33-
protected val b_tgt = io.pc + io.imm.B
34-
protected val jal_tgt = io.pc + io.imm.J
35-
protected val jalr_tgt = io.src1 + io.imm.I
33+
protected val b_tgt = io.pc + io.imm
34+
protected val jal_tgt = io.pc + io.imm
35+
protected val jalr_tgt = io.src1 + io.imm
3636

3737
io.branch := b | jal | jalr
3838

‎rtl/tc_l2/src/main/scala/core/exec/EXU.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ class EXU extends Module {
6868
protected val tgt = beu.io.tgt
6969

7070
protected val link = SignExt((isa.JAL | isa.JALR).asUInt, 64) & (pc + 4.U)
71-
protected val auipc = SignExt(isa.AUIPC.asUInt, 64) & (pc + imm.U)
71+
protected val auipc = SignExt(isa.AUIPC.asUInt, 64) & (pc + imm)
7272

7373
protected val csrReg = Module(new CSRReg)
7474
protected val csrData = csrReg.io.data

‎rtl/tc_l2/src/main/scala/core/id/ISADecoder.scala‎

Lines changed: 160 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -113,89 +113,89 @@ class ISADecoder extends Module with InstConfig {
113113
val io = IO(new Bundle {
114114
val inst = Input(UInt(InstLen.W))
115115
val isa = Output(new ISAIO)
116-
val imm = Output(new IMMIO)
116+
val imm = Output(UInt(XLen.W))
117117
val csr = Output(new Bool())
118118
val wen = Output(new Bool())
119119
})
120120

121-
io.isa.SLLI := (io.inst === ISADecoder.SLLI )
122-
io.isa.SLLIW := (io.inst === ISADecoder.SLLIW )
123-
io.isa.SRLI := (io.inst === ISADecoder.SRLI )
124-
io.isa.SRLIW := (io.inst === ISADecoder.SRLIW )
125-
io.isa.SRAI := (io.inst === ISADecoder.SRAI )
126-
io.isa.SRAIW := (io.inst === ISADecoder.SRAIW )
127-
io.isa.ADDI := (io.inst === ISADecoder.ADDI )
128-
io.isa.ADDIW := (io.inst === ISADecoder.ADDIW )
129-
io.isa.XORI := (io.inst === ISADecoder.XORI )
130-
io.isa.ORI := (io.inst === ISADecoder.ORI )
131-
io.isa.ANDI := (io.inst === ISADecoder.ANDI )
132-
io.isa.SLTI := (io.inst === ISADecoder.SLTI )
133-
io.isa.SLTIU := (io.inst === ISADecoder.SLTIU )
134-
io.isa.JALR := (io.inst === ISADecoder.JALR )
135-
io.isa.FENCE := (io.inst === ISADecoder.FENCE )
136-
io.isa.FENCE_I := (io.inst === ISADecoder.FENCE_I )
137-
io.isa.ECALL := (io.inst === ISADecoder.ECALL )
138-
io.isa.EBREAK := (io.inst === ISADecoder.EBREAK )
139-
io.isa.CSRRW := (io.inst === ISADecoder.CSRRW )
140-
io.isa.CSRRWI := (io.inst === ISADecoder.CSRRWI )
141-
io.isa.CSRRS := (io.inst === ISADecoder.CSRRS )
142-
io.isa.CSRRSI := (io.inst === ISADecoder.CSRRSI )
143-
io.isa.CSRRC := (io.inst === ISADecoder.CSRRC )
144-
io.isa.CSRRCI := (io.inst === ISADecoder.CSRRCI )
145-
io.isa.LD := (io.inst === ISADecoder.LD )
146-
io.isa.LW := (io.inst === ISADecoder.LW )
147-
io.isa.LWU := (io.inst === ISADecoder.LWU )
148-
io.isa.LH := (io.inst === ISADecoder.LH )
149-
io.isa.LHU := (io.inst === ISADecoder.LHU )
150-
io.isa.LB := (io.inst === ISADecoder.LB )
151-
io.isa.LBU := (io.inst === ISADecoder.LBU )
152-
io.isa.SLL := (io.inst === ISADecoder.SLL )
153-
io.isa.SLLW := (io.inst === ISADecoder.SLLW )
154-
io.isa.SRL := (io.inst === ISADecoder.SRL )
155-
io.isa.SRLW := (io.inst === ISADecoder.SRLW )
156-
io.isa.SRA := (io.inst === ISADecoder.SRA )
157-
io.isa.SRAW := (io.inst === ISADecoder.SRAW )
158-
io.isa.ADD := (io.inst === ISADecoder.ADD )
159-
io.isa.ADDW := (io.inst === ISADecoder.ADDW )
160-
io.isa.SUB := (io.inst === ISADecoder.SUB )
161-
io.isa.SUBW := (io.inst === ISADecoder.SUBW )
162-
io.isa.XOR := (io.inst === ISADecoder.XOR )
163-
io.isa.OR := (io.inst === ISADecoder.OR )
164-
io.isa.AND := (io.inst === ISADecoder.AND )
165-
io.isa.SLT := (io.inst === ISADecoder.SLT )
166-
io.isa.SLTU := (io.inst === ISADecoder.SLTU )
167-
io.isa.MRET := (io.inst === ISADecoder.MRET )
168-
io.isa.SRET := (io.inst === ISADecoder.SRET )
169-
io.isa.WFI := (io.inst === ISADecoder.WFI )
121+
io.isa.SLLI := (io.inst === ISADecoder.SLLI)
122+
io.isa.SLLIW := (io.inst === ISADecoder.SLLIW)
123+
io.isa.SRLI := (io.inst === ISADecoder.SRLI)
124+
io.isa.SRLIW := (io.inst === ISADecoder.SRLIW)
125+
io.isa.SRAI := (io.inst === ISADecoder.SRAI)
126+
io.isa.SRAIW := (io.inst === ISADecoder.SRAIW)
127+
io.isa.ADDI := (io.inst === ISADecoder.ADDI)
128+
io.isa.ADDIW := (io.inst === ISADecoder.ADDIW)
129+
io.isa.XORI := (io.inst === ISADecoder.XORI)
130+
io.isa.ORI := (io.inst === ISADecoder.ORI)
131+
io.isa.ANDI := (io.inst === ISADecoder.ANDI)
132+
io.isa.SLTI := (io.inst === ISADecoder.SLTI)
133+
io.isa.SLTIU := (io.inst === ISADecoder.SLTIU)
134+
io.isa.JALR := (io.inst === ISADecoder.JALR)
135+
io.isa.FENCE := (io.inst === ISADecoder.FENCE)
136+
io.isa.FENCE_I := (io.inst === ISADecoder.FENCE_I)
137+
io.isa.ECALL := (io.inst === ISADecoder.ECALL)
138+
io.isa.EBREAK := (io.inst === ISADecoder.EBREAK)
139+
io.isa.CSRRW := (io.inst === ISADecoder.CSRRW)
140+
io.isa.CSRRWI := (io.inst === ISADecoder.CSRRWI)
141+
io.isa.CSRRS := (io.inst === ISADecoder.CSRRS)
142+
io.isa.CSRRSI := (io.inst === ISADecoder.CSRRSI)
143+
io.isa.CSRRC := (io.inst === ISADecoder.CSRRC)
144+
io.isa.CSRRCI := (io.inst === ISADecoder.CSRRCI)
145+
io.isa.LD := (io.inst === ISADecoder.LD)
146+
io.isa.LW := (io.inst === ISADecoder.LW)
147+
io.isa.LWU := (io.inst === ISADecoder.LWU)
148+
io.isa.LH := (io.inst === ISADecoder.LH)
149+
io.isa.LHU := (io.inst === ISADecoder.LHU)
150+
io.isa.LB := (io.inst === ISADecoder.LB)
151+
io.isa.LBU := (io.inst === ISADecoder.LBU)
152+
io.isa.SLL := (io.inst === ISADecoder.SLL)
153+
io.isa.SLLW := (io.inst === ISADecoder.SLLW)
154+
io.isa.SRL := (io.inst === ISADecoder.SRL)
155+
io.isa.SRLW := (io.inst === ISADecoder.SRLW)
156+
io.isa.SRA := (io.inst === ISADecoder.SRA)
157+
io.isa.SRAW := (io.inst === ISADecoder.SRAW)
158+
io.isa.ADD := (io.inst === ISADecoder.ADD)
159+
io.isa.ADDW := (io.inst === ISADecoder.ADDW)
160+
io.isa.SUB := (io.inst === ISADecoder.SUB)
161+
io.isa.SUBW := (io.inst === ISADecoder.SUBW)
162+
io.isa.XOR := (io.inst === ISADecoder.XOR)
163+
io.isa.OR := (io.inst === ISADecoder.OR)
164+
io.isa.AND := (io.inst === ISADecoder.AND)
165+
io.isa.SLT := (io.inst === ISADecoder.SLT)
166+
io.isa.SLTU := (io.inst === ISADecoder.SLTU)
167+
io.isa.MRET := (io.inst === ISADecoder.MRET)
168+
io.isa.SRET := (io.inst === ISADecoder.SRET)
169+
io.isa.WFI := (io.inst === ISADecoder.WFI)
170170
io.isa.SFENCE_VMA := (io.inst === ISADecoder.SFENCE_VMA)
171-
io.isa.BEQ := (io.inst === ISADecoder.BEQ )
172-
io.isa.BNE := (io.inst === ISADecoder.BNE )
173-
io.isa.BLT := (io.inst === ISADecoder.BLT )
174-
io.isa.BGE := (io.inst === ISADecoder.BGE )
175-
io.isa.BLTU := (io.inst === ISADecoder.BLTU )
176-
io.isa.BGEU := (io.inst === ISADecoder.BGEU )
177-
io.isa.SD := (io.inst === ISADecoder.SD )
178-
io.isa.SW := (io.inst === ISADecoder.SW )
179-
io.isa.SH := (io.inst === ISADecoder.SH )
180-
io.isa.SB := (io.inst === ISADecoder.SB )
181-
io.isa.LUI := (io.inst === ISADecoder.LUI )
182-
io.isa.AUIPC := (io.inst === ISADecoder.AUIPC )
183-
io.isa.JAL := (io.inst === ISADecoder.JAL )
184-
185-
io.isa.MUL := (io.inst === BitPat("b0000001_?????_?????_000_?????_0110011"))
186-
io.isa.MULH := (io.inst === BitPat("b0000001_?????_?????_001_?????_0110011"))
187-
io.isa.MULHSU := (io.inst === BitPat("b0000001_?????_?????_010_?????_0110011"))
188-
io.isa.MULHU := (io.inst === BitPat("b0000001_?????_?????_011_?????_0110011"))
189-
io.isa.MULW := (io.inst === BitPat("b0000001_?????_?????_000_?????_0111011"))
190-
io.isa.DIV := (io.inst === BitPat("b0000001_?????_?????_100_?????_0110011"))
191-
io.isa.DIVU := (io.inst === BitPat("b0000001_?????_?????_101_?????_0110011"))
192-
io.isa.DIVUW := (io.inst === BitPat("b0000001_?????_?????_101_?????_0111011"))
193-
io.isa.DIVW := (io.inst === BitPat("b0000001_?????_?????_100_?????_0111011"))
194-
io.isa.REM := (io.inst === BitPat("b0000001_?????_?????_110_?????_0110011"))
195-
io.isa.REMU := (io.inst === BitPat("b0000001_?????_?????_111_?????_0110011"))
196-
io.isa.REMUW := (io.inst === BitPat("b0000001_?????_?????_111_?????_0111011"))
197-
io.isa.REMW := (io.inst === BitPat("b0000001_?????_?????_110_?????_0111011"))
198-
io.isa.GCD := (io.inst === BitPat("b0000000_?????_?????_000_?????_0001000"))
171+
io.isa.BEQ := (io.inst === ISADecoder.BEQ)
172+
io.isa.BNE := (io.inst === ISADecoder.BNE)
173+
io.isa.BLT := (io.inst === ISADecoder.BLT)
174+
io.isa.BGE := (io.inst === ISADecoder.BGE)
175+
io.isa.BLTU := (io.inst === ISADecoder.BLTU)
176+
io.isa.BGEU := (io.inst === ISADecoder.BGEU)
177+
io.isa.SD := (io.inst === ISADecoder.SD)
178+
io.isa.SW := (io.inst === ISADecoder.SW)
179+
io.isa.SH := (io.inst === ISADecoder.SH)
180+
io.isa.SB := (io.inst === ISADecoder.SB)
181+
io.isa.LUI := (io.inst === ISADecoder.LUI)
182+
io.isa.AUIPC := (io.inst === ISADecoder.AUIPC)
183+
io.isa.JAL := (io.inst === ISADecoder.JAL)
184+
185+
io.isa.MUL := (io.inst === BitPat("b0000001_?????_?????_000_?????_0110011"))
186+
io.isa.MULH := (io.inst === BitPat("b0000001_?????_?????_001_?????_0110011"))
187+
io.isa.MULHSU := (io.inst === BitPat("b0000001_?????_?????_010_?????_0110011"))
188+
io.isa.MULHU := (io.inst === BitPat("b0000001_?????_?????_011_?????_0110011"))
189+
io.isa.MULW := (io.inst === BitPat("b0000001_?????_?????_000_?????_0111011"))
190+
io.isa.DIV := (io.inst === BitPat("b0000001_?????_?????_100_?????_0110011"))
191+
io.isa.DIVU := (io.inst === BitPat("b0000001_?????_?????_101_?????_0110011"))
192+
io.isa.DIVUW := (io.inst === BitPat("b0000001_?????_?????_101_?????_0111011"))
193+
io.isa.DIVW := (io.inst === BitPat("b0000001_?????_?????_100_?????_0111011"))
194+
io.isa.REM := (io.inst === BitPat("b0000001_?????_?????_110_?????_0110011"))
195+
io.isa.REMU := (io.inst === BitPat("b0000001_?????_?????_111_?????_0110011"))
196+
io.isa.REMUW := (io.inst === BitPat("b0000001_?????_?????_111_?????_0111011"))
197+
io.isa.REMW := (io.inst === BitPat("b0000001_?????_?????_110_?????_0111011"))
198+
io.isa.GCD := (io.inst === BitPat("b0000000_?????_?????_000_?????_0001000"))
199199

200200
protected val arith = io.isa.ADD || io.isa.ADDW || io.isa.ADDI || io.isa.ADDIW || io.isa.SUB || io.isa.SUBW || io.isa.LUI || io.isa.AUIPC
201201
protected val logc = io.isa.XOR || io.isa.XORI || io.isa.OR || io.isa.ORI || io.isa.AND || io.isa.ANDI
@@ -211,9 +211,87 @@ class ISADecoder extends Module with InstConfig {
211211
protected val priv = io.isa.MRET || io.isa.SRET || io.isa.WFI || io.isa.SFENCE_VMA
212212
protected val custom = io.isa.GCD
213213

214+
protected val decodeTable = Array(
215+
// i type inst
216+
ISADecoder.ADDI -> List(iInstType),
217+
ISADecoder.ADDIW -> List(iInstType),
218+
ISADecoder.SLTI -> List(iInstType),
219+
ISADecoder.SLTIU -> List(iInstType),
220+
ISADecoder.ANDI -> List(iInstType),
221+
ISADecoder.ORI -> List(iInstType),
222+
ISADecoder.XORI -> List(iInstType),
223+
ISADecoder.SLLI -> List(iInstType),
224+
ISADecoder.SLLIW -> List(iInstType),
225+
ISADecoder.SRLI -> List(iInstType),
226+
ISADecoder.SRLIW -> List(iInstType),
227+
ISADecoder.SRAI -> List(iInstType),
228+
ISADecoder.SRAIW -> List(iInstType),
229+
// u type inst
230+
ISADecoder.LUI -> List(uInstType),
231+
ISADecoder.AUIPC -> List(uInstType),
232+
// r type inst
233+
ISADecoder.ADD -> List(rInstType),
234+
ISADecoder.ADDW -> List(rInstType),
235+
ISADecoder.SLT -> List(rInstType),
236+
ISADecoder.SLTU -> List(rInstType),
237+
ISADecoder.AND -> List(rInstType),
238+
ISADecoder.OR -> List(rInstType),
239+
ISADecoder.XOR -> List(rInstType),
240+
ISADecoder.SLL -> List(rInstType),
241+
ISADecoder.SLLW -> List(rInstType),
242+
ISADecoder.SRL -> List(rInstType),
243+
ISADecoder.SRLW -> List(rInstType),
244+
ISADecoder.SUB -> List(rInstType),
245+
ISADecoder.SUBW -> List(rInstType),
246+
ISADecoder.SRA -> List(rInstType),
247+
ISADecoder.SRAW -> List(rInstType),
248+
// nop inst
249+
ISADecoder.NOP -> List(nopInstType),
250+
// j type inst
251+
ISADecoder.JAL -> List(jInstType),
252+
ISADecoder.JALR -> List(iInstType),
253+
// b type inst
254+
ISADecoder.BEQ -> List(bInstType),
255+
ISADecoder.BNE -> List(bInstType),
256+
ISADecoder.BLT -> List(bInstType),
257+
ISADecoder.BLTU -> List(bInstType),
258+
ISADecoder.BGE -> List(bInstType),
259+
ISADecoder.BGEU -> List(bInstType),
260+
// special i type inst
261+
ISADecoder.LB -> List(iInstType),
262+
ISADecoder.LBU -> List(iInstType),
263+
ISADecoder.LH -> List(iInstType),
264+
ISADecoder.LHU -> List(iInstType),
265+
ISADecoder.LW -> List(iInstType),
266+
ISADecoder.LWU -> List(iInstType),
267+
ISADecoder.LD -> List(iInstType),
268+
// s type inst
269+
ISADecoder.SB -> List(sInstType),
270+
ISADecoder.SH -> List(sInstType),
271+
ISADecoder.SW -> List(sInstType),
272+
ISADecoder.SD -> List(sInstType),
273+
// csr inst
274+
ISADecoder.CSRRW -> List(iInstType),
275+
ISADecoder.CSRRS -> List(iInstType),
276+
ISADecoder.CSRRC -> List(iInstType),
277+
ISADecoder.CSRRWI -> List(iInstType),
278+
ISADecoder.CSRRSI -> List(iInstType),
279+
ISADecoder.CSRRCI -> List(iInstType),
280+
// system inst
281+
ISADecoder.ECALL -> List(nopInstType),
282+
ISADecoder.MRET -> List(nopInstType),
283+
ISADecoder.FENCE -> List(nopInstType),
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ISADecoder.FENCE_I -> List(nopInstType),
285+
// custom inst
286+
ISADecoder.CUST -> List(nopInstType)
287+
)
288+
214289
protected val immExten = Module(new ImmExten)
215-
immExten.io.inst := io.inst
216-
io.imm := immExten.io.imm
217-
io.csr := csr
218-
io.wen := arith || logc || shift || comp || link || load || csr || custom
290+
protected val defRes = List(nopInstType)
291+
292+
immExten.io.inst := io.inst
293+
immExten.io.instType := ListLookup(io.inst, defRes, decodeTable)(0)
294+
io.imm := immExten.io.imm
295+
io.csr := csr
296+
io.wen := arith || logc || shift || comp || link || load || csr || custom
219297
}

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