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maksyukimaksyuki
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Merge branch 'tc-l3' into dev
2 parents a5dfc98 + f04a642 commit 9de3bb8

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10 files changed

+384
-33
lines changed

10 files changed

+384
-33
lines changed

‎rtl/.scalafmt.conf‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ assumeStandardLibraryStripMargin = true
77
docstrings = ScalaDoc
88
lineEndings = preserve
99
includeCurlyBraceInSelectChains = false
10-
danglingParentheses = true
10+
danglingParentheses.preset = true
1111

1212
align.tokens.add = [
1313
{

‎rtl/build.sc‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,14 +12,14 @@ object tc_l2 extends ScalaModule with ScalafmtModule { m =>
1212
"-deprecation",
1313
"-feature",
1414
"-Xcheckinit",
15-
// Enables autoclonetype2 in 3.4.x (on by default in 3.5)
16-
"-P:chiselplugin:useBundlePlugin"
15+
// Enables autoclonetype2 in 3.4.x (on by default in 3.5.0)
16+
// "-P:chiselplugin:useBundlePlugin"
1717
)
1818
override def ivyDeps = Agg(
19-
ivy"edu.berkeley.cs::chisel3:3.4.3",
19+
ivy"edu.berkeley.cs::chisel3:3.5.0",
2020
)
2121
override def scalacPluginIvyDeps = Agg(
22-
ivy"edu.berkeley.cs:::chisel3-plugin:3.4.3",
22+
ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0",
2323
ivy"org.scalamacros:::paradise:2.1.1"
2424
)
2525
object test extends Tests with Utest {
@@ -40,14 +40,14 @@ object tc_l3 extends ScalaModule with ScalafmtModule { m =>
4040
"-deprecation",
4141
"-feature",
4242
"-Xcheckinit",
43-
// Enables autoclonetype2 in 3.4.x (on by default in 3.5)
44-
"-P:chiselplugin:useBundlePlugin"
43+
// Enables autoclonetype2 in 3.4.x (on by default in 3.5.0)
44+
// "-P:chiselplugin:useBundlePlugin"
4545
)
4646
override def ivyDeps = Agg(
47-
ivy"edu.berkeley.cs::chisel3:3.4.3",
47+
ivy"edu.berkeley.cs::chisel3:3.5.0",
4848
)
4949
override def scalacPluginIvyDeps = Agg(
50-
ivy"edu.berkeley.cs:::chisel3-plugin:3.4.3",
50+
ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0",
5151
ivy"org.scalamacros:::paradise:2.1.1"
5252
)
5353
object test extends Tests with Utest {
@@ -64,6 +64,6 @@ object difftest extends ScalaModule {
6464
override def scalaVersion = "2.12.13"
6565
override def millSourcePath = os.pwd / "dependency" / "difftest"
6666
override def ivyDeps = Agg(
67-
ivy"edu.berkeley.cs::chisel3:3.4.3"
67+
ivy"edu.berkeley.cs::chisel3:3.5.0"
6868
)
6969
}

‎rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,11 @@ class AXI4Bridge extends Module with InstConfig {
1515
arbiter.io.runEn <> io.runEn
1616
arbiter.io.dxchg <> io.dxchg
1717
arbiter.io.axirdata := io.axi.r.bits.data
18-
arbiter.io.awHdShk := io.axi.aw.fire()
19-
arbiter.io.wHdShk := io.axi.w.fire()
20-
arbiter.io.bHdShk := io.axi.b.fire()
21-
arbiter.io.arHdShk := io.axi.ar.fire()
22-
arbiter.io.rHdShk := io.axi.r.fire()
18+
arbiter.io.awHdShk := io.axi.aw.fire
19+
arbiter.io.wHdShk := io.axi.w.fire
20+
arbiter.io.bHdShk := io.axi.b.fire
21+
arbiter.io.arHdShk := io.axi.ar.fire
22+
arbiter.io.rHdShk := io.axi.r.fire
2323

2424
protected val wMask = arbiter.io.dxchg.wmask
2525
protected val socARSize = arbiter.io.dxchg.rsize

‎rtl/tc_l2/src/main/scala/axi4/Crossbar.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ class Crossbar extends Module with InstConfig {
5252
io.dxchg.ren := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
5353
io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, ldAddr)
5454
io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
55-
io.dxchg.wen := stateReg === eumMem && io.core.sd.en
55+
io.dxchg.wen := stateReg === eumMem && io.core.sd.en
5656
io.dxchg.waddr := sdAddr
5757
io.dxchg.wdata := io.core.sd.data
5858
io.dxchg.wmask := io.core.sd.mask

‎rtl/tc_l2/src/main/scala/core/exec/CSRReg.scala‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -45,16 +45,16 @@ class CSRReg extends Module with InstConfig {
4545
protected val addr = io.inst(31, 20)
4646
protected val mretVis = io.inst === instMRET
4747
protected val ecallVis = io.inst === instECALL
48-
protected val mhartidVis = addr === mhartidAddr
49-
protected val mstatusVis = addr === mstatusAddr
50-
protected val mieVis = addr === mieAddr
51-
protected val mtvecVis = addr === mtvecAddr
52-
protected val mscratchVis = addr === mscratchAddr
53-
protected val mepcVis = addr === mepcAddr
54-
protected val mcauseVis = addr === mcauseAddr
55-
protected val mipVis = addr === mipAddr
56-
protected val mcycleVis = addr === mcycleAddr
57-
protected val medelegVis = addr === medelegAddr
48+
protected val mhartidVis = addr === mhartidAddr
49+
protected val mstatusVis = addr === mstatusAddr
50+
protected val mieVis = addr === mieAddr
51+
protected val mtvecVis = addr === mtvecAddr
52+
protected val mscratchVis = addr === mscratchAddr
53+
protected val mepcVis = addr === mepcAddr
54+
protected val mcauseVis = addr === mcauseAddr
55+
protected val mipVis = addr === mipAddr
56+
protected val mcycleVis = addr === mcycleAddr
57+
protected val medelegVis = addr === medelegAddr
5858

5959
protected val rdVal = MuxLookup(
6060
addr,

‎rtl/tc_l2/src/main/scala/core/exec/EXU.scala‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@ class EXU extends Module with InstConfig {
3232
// handle bypass signal
3333
protected val bypassMemSrc1En = io.bypassMem.wen && (rs1 === io.bypassMem.wdest) && (rs1 =/= 0.U)
3434
protected val bypassMemSrc2En = io.bypassMem.wen && (rs2 === io.bypassMem.wdest) && (rs2 =/= 0.U)
35-
protected val bypassWbSrc1En = io.bypassWb.wen && (rs1 === io.bypassWb.wdest) && (rs1 =/= 0.U)
36-
protected val bypassWbSrc2En = io.bypassWb.wen && (rs2 === io.bypassWb.wdest) && (rs2 =/= 0.U)
35+
protected val bypassWbSrc1En = io.bypassWb.wen && (rs1 === io.bypassWb.wdest) && (rs1 =/= 0.U)
36+
protected val bypassWbSrc2En = io.bypassWb.wen && (rs2 === io.bypassWb.wdest) && (rs2 =/= 0.U)
3737
protected val src1 = Mux(bypassMemSrc1En, io.bypassMem.data, Mux(bypassWbSrc1En, io.bypassWb.data, exReg.src1))
3838
protected val src2 = Mux(bypassMemSrc2En, io.bypassMem.data, Mux(bypassWbSrc2En, io.bypassWb.data, exReg.src2))
3939

@@ -82,12 +82,12 @@ class EXU extends Module with InstConfig {
8282

8383
io.nxtPC.trap := valid && (timeIntrEn || ecallEn)
8484
io.nxtPC.mtvec := csrReg.io.csrState.mtvec
85-
io.nxtPC.mret := valid && (isa === instMRET)
85+
io.nxtPC.mret := valid && (isa === instMRET)
8686
io.nxtPC.mepc := csrReg.io.csrState.mepc
8787
// (pred, fact)--->(NT, T) or (T, NT)
88-
protected val predNTfactT = branch && !predTaken
88+
protected val predNTfactT = branch && !predTaken
8989
protected val predTfactNT = !branch && predTaken
90-
io.nxtPC.branch := valid && (predNTfactT || predTfactNT)
90+
io.nxtPC.branch := valid && (predNTfactT || predTfactNT)
9191
io.nxtPC.tgt := Mux(valid && predNTfactT, tgt, Mux(valid && predTfactNT, pc + 4.U, 0.U(XLen.W)))
9292
io.stall := valid && (io.nxtPC.branch || timeIntrEn || ecallEn || (isa === instMRET))
9393

‎rtl/tc_l2/src/main/scala/core/ma/CLINT.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ class CLINT extends Module with InstConfig {
2323
// check if a mmio access
2424
protected val cren = io.cld.en && (mtimecmpVis || mtimeVis) && io.valid
2525
protected val cwen = io.csd.en && (mtimecmpVis || mtimeVis) && io.valid
26-
protected val cvalid = cren || cwen
26+
protected val cvalid = cren || cwen
2727

2828
// generate low speed clock
2929
protected val (tickCnt, cntWrap) = Counter(true.B, 5)

‎rtl/tc_l2/src/main/scala/utils/AddModulePrefix.scala‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,8 @@ class AddModulePrefix extends Transform with DependencyAPIMigration {
4343
else if (extModules.contains(old)) old
4444
else prefix + old
4545

46-
val renameMap = RenameMap()
46+
// val renameMap = RenameMap()
47+
val renameMap = firrtl.renamemap.MutableRenameMap() // for firrtl 1.5 under the chisel 3.5.x
4748

4849
def onStmt(s: Statement): Statement = s match {
4950
case DefInstance(info, name, module, tpe) =>

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