|
| 1 | +package treecorel3 |
| 2 | + |
| 3 | +import chisel3._ |
| 4 | +import chisel3.util._ |
| 5 | + |
| 6 | +class SOCAXI4ARWIO extends Bundle with AXI4Config { |
| 7 | + val addr = Output(UInt(32.W)) |
| 8 | + val id = Output(UInt(AxiIdLen.W)) |
| 9 | + val len = Output(UInt(AxiLen.W)) |
| 10 | + val size = Output(UInt(AxiSizeLen.W)) |
| 11 | + val burst = Output(UInt(AxiBurstLen.W)) |
| 12 | +} |
| 13 | + |
| 14 | +class AXI4ARWIO extends SOCAXI4ARWIO { |
| 15 | + override val addr = Output(UInt(XLen.W)) |
| 16 | + val prot = Output(UInt(AxiProtLen.W)) |
| 17 | + val user = Output(UInt(AxiUserLen.W)) |
| 18 | + val lock = Output(Bool()) |
| 19 | + val cache = Output(UInt(AxiCacheLen.W)) |
| 20 | + val qos = Output(UInt(AxiQosLen.W)) |
| 21 | +} |
| 22 | + |
| 23 | +class SOCAXI4WIO extends Bundle with AXI4Config { |
| 24 | + val data = Output(UInt(XLen.W)) |
| 25 | + val strb = Output(UInt(AxiStrb.W)) |
| 26 | + val last = Output(Bool()) |
| 27 | +} |
| 28 | + |
| 29 | +class AXI4WIO extends SOCAXI4WIO {} |
| 30 | + |
| 31 | +class SOCAXI4BIO extends Bundle with AXI4Config { |
| 32 | + val resp = Output(UInt(AxiRespLen.W)) |
| 33 | + val id = Output(UInt(AxiIdLen.W)) |
| 34 | +} |
| 35 | + |
| 36 | +class AXI4BIO extends SOCAXI4BIO { |
| 37 | + val user = Output(UInt(AxiUserLen.W)) |
| 38 | +} |
| 39 | + |
| 40 | +class SOCAXI4RIO extends Bundle with AXI4Config { |
| 41 | + val resp = Output(UInt(AxiRespLen.W)) |
| 42 | + val data = Output(UInt(XLen.W)) |
| 43 | + val last = Output(Bool()) |
| 44 | + val id = Output(UInt(AxiIdLen.W)) |
| 45 | +} |
| 46 | + |
| 47 | +class AXI4RIO extends SOCAXI4RIO { |
| 48 | + val user = Output(UInt(AxiUserLen.W)) |
| 49 | +} |
| 50 | + |
| 51 | +class SOCAXI4IO extends Bundle { |
| 52 | + val aw = Decoupled(new SOCAXI4ARWIO) |
| 53 | + val w = Decoupled(new SOCAXI4WIO) |
| 54 | + val b = Flipped(Decoupled(new SOCAXI4BIO)) |
| 55 | + val ar = Decoupled(new SOCAXI4ARWIO) |
| 56 | + val r = Flipped(Decoupled(new SOCAXI4RIO)) |
| 57 | +} |
| 58 | + |
| 59 | +class AXI4IO extends SOCAXI4IO { |
| 60 | + override val aw = Decoupled(new AXI4ARWIO) |
| 61 | + override val w = Decoupled(new AXI4WIO) |
| 62 | + override val b = Flipped(Decoupled(new AXI4BIO)) |
| 63 | + override val ar = Decoupled(new AXI4ARWIO) |
| 64 | + override val r = Flipped(Decoupled(new AXI4RIO)) |
| 65 | +} |
0 commit comments