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maksyukimaksyuki
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style: change if, id, ex and ma stage's name
1 parent 101c6f1 commit b8553db

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‎rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala‎

Lines changed: 99 additions & 99 deletions
Original file line numberDiff line numberDiff line change
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package treecorel2
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import chisel3._
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import chisel3.util._
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import difftest._
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class TreeCoreL2 extends Module {
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val io = IO(new Bundle {
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val globalEn = Input(Bool())
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val socEn = Input(Bool())
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val fetch = new IFIO
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val ld = new LDIO
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val sd = new SDIO
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// difftest
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val instComm = Flipped(new DiffInstrCommitIO)
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val archIntRegState = Flipped(new DiffArchIntRegStateIO)
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val csrState = Flipped(new DiffCSRStateIO)
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val trapEvt = Flipped(new DiffTrapEventIO)
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val archFpRegState = Flipped(new DiffArchFpRegStateIO)
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val archEvt = Flipped(new DiffArchEventIO)
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})
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protected val ifUnit = Module(new IFU)
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protected val idUnit = Module(new InstDecode)
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protected val execUnit = Module(new EXU)
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protected val maUnit = Module(new Memory)
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protected val wbUnit = Module(new WriteBack)
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ifUnit.io.socEn := io.socEn
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wbUnit.io.socEn := io.socEn
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// datapath
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ifUnit.io.if2id <> idUnit.io.if2id
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idUnit.io.id2ex <> execUnit.io.id2ex
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execUnit.io.ex2mem <> maUnit.io.ex2mem
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maUnit.io.mem2wb <> wbUnit.io.mem2wb
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execUnit.io.stall <> idUnit.io.stall
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execUnit.io.stall <> ifUnit.io.stall
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// bypass
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idUnit.io.wbdata <> wbUnit.io.wbdata
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execUnit.io.bypassMem <> maUnit.io.bypassMem
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execUnit.io.bypassWb <> wbUnit.io.wbdata
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execUnit.io.nxtPC <> ifUnit.io.nxtPC
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execUnit.io.mtip <> maUnit.io.mtip
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protected val isStall = execUnit.io.stall
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protected val (tickCnt, cntWrap) = Counter(io.globalEn && isStall, 3)
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protected val stallCycle1 = isStall && (tickCnt === 0.U)
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protected val stallCycle2 = isStall && (tickCnt === 1.U)
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protected val stallCycle3 = isStall && (tickCnt === 2.U)
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ifUnit.io.stall := stallCycle1
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idUnit.io.stall := stallCycle1
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ifUnit.io.globalEn := io.globalEn
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idUnit.io.globalEn := io.globalEn
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execUnit.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
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maUnit.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
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wbUnit.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
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idUnit.io.wbdata := Mux(stallCycle1 || stallCycle2, 0.U.asTypeOf(new WBDATAIO), wbUnit.io.wbdata)
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ifUnit.io.nxtPC := Mux(stallCycle1, execUnit.io.nxtPC, 0.U.asTypeOf(new NXTPCIO))
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protected val ldDataInStall = RegInit(0.U(64.W))
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when(io.globalEn) {
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when(stallCycle1) {
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ldDataInStall := io.ld.data
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}.elsewhen(stallCycle3) {
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ldDataInStall := 0.U
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}
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}
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// communicate with extern io
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io.fetch <> ifUnit.io.fetch
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//Even load can change machine state
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protected val lsStall = RegEnable(stallCycle1, false.B, io.globalEn) || RegEnable(stallCycle2, false.B, io.globalEn)
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io.ld.en := maUnit.io.ld.en && ~lsStall
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io.ld.addr := maUnit.io.ld.addr
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maUnit.io.ld.data := Mux(lsStall, ldDataInStall, io.ld.data)
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io.ld.size := maUnit.io.ld.size
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io.sd.en := maUnit.io.sd.en && ~lsStall
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io.sd.addr := maUnit.io.sd.addr
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io.sd.data := maUnit.io.sd.data
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io.sd.mask := maUnit.io.sd.mask
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idUnit.io.gpr <> wbUnit.io.gpr
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io.instComm <> wbUnit.io.instComm
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io.archIntRegState <> wbUnit.io.archIntRegState
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io.csrState <> wbUnit.io.csrState
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io.trapEvt <> wbUnit.io.trapEvt
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io.archFpRegState <> wbUnit.io.archFpRegState
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io.archEvt <> wbUnit.io.archEvt
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}
1+
package treecorel2
2+
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import chisel3._
4+
import chisel3.util._
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import difftest._
6+
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class TreeCoreL2 extends Module {
8+
val io = IO(new Bundle {
9+
val globalEn = Input(Bool())
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val socEn = Input(Bool())
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val fetch = new IFIO
12+
val ld = new LDIO
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val sd = new SDIO
14+
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// difftest
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val instComm = Flipped(new DiffInstrCommitIO)
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val archIntRegState = Flipped(new DiffArchIntRegStateIO)
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val csrState = Flipped(new DiffCSRStateIO)
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val trapEvt = Flipped(new DiffTrapEventIO)
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val archFpRegState = Flipped(new DiffArchFpRegStateIO)
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val archEvt = Flipped(new DiffArchEventIO)
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})
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protected val ifu = Module(new IFU)
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protected val idu = Module(new IDU)
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protected val exu = Module(new EXU)
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protected val mau = Module(new Memory)
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protected val wbu = Module(new WriteBack)
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ifu.io.socEn := io.socEn
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wbu.io.socEn := io.socEn
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// datapath
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ifu.io.if2id <> idu.io.if2id
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idu.io.id2ex <> exu.io.id2ex
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exu.io.ex2mem <> mau.io.ex2mem
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mau.io.mem2wb <> wbu.io.mem2wb
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exu.io.stall <> idu.io.stall
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exu.io.stall <> ifu.io.stall
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// bypass
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idu.io.wbdata <> wbu.io.wbdata
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exu.io.bypassMem <> mau.io.bypassMem
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exu.io.bypassWb <> wbu.io.wbdata
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exu.io.nxtPC <> ifu.io.nxtPC
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exu.io.mtip <> mau.io.mtip
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protected val isStall = exu.io.stall
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protected val (tickCnt, cntWrap) = Counter(io.globalEn && isStall, 3)
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protected val stallCycle1 = isStall && (tickCnt === 0.U)
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protected val stallCycle2 = isStall && (tickCnt === 1.U)
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protected val stallCycle3 = isStall && (tickCnt === 2.U)
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ifu.io.stall := stallCycle1
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idu.io.stall := stallCycle1
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ifu.io.globalEn := io.globalEn
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idu.io.globalEn := io.globalEn
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exu.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
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mau.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
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wbu.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
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idu.io.wbdata := Mux(stallCycle1 || stallCycle2, 0.U.asTypeOf(new WBDATAIO), wbu.io.wbdata)
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ifu.io.nxtPC := Mux(stallCycle1, exu.io.nxtPC, 0.U.asTypeOf(new NXTPCIO))
66+
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protected val ldDataInStall = RegInit(0.U(64.W))
68+
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when(io.globalEn) {
70+
when(stallCycle1) {
71+
ldDataInStall := io.ld.data
72+
}.elsewhen(stallCycle3) {
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ldDataInStall := 0.U
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}
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}
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// communicate with extern io
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io.fetch <> ifu.io.fetch
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//Even load can change machine state
81+
protected val lsStall = RegEnable(stallCycle1, false.B, io.globalEn) || RegEnable(stallCycle2, false.B, io.globalEn)
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io.ld.en := mau.io.ld.en && ~lsStall
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io.ld.addr := mau.io.ld.addr
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mau.io.ld.data := Mux(lsStall, ldDataInStall, io.ld.data)
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io.ld.size := mau.io.ld.size
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io.sd.en := mau.io.sd.en && ~lsStall
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io.sd.addr := mau.io.sd.addr
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io.sd.data := mau.io.sd.data
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io.sd.mask := mau.io.sd.mask
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idu.io.gpr <> wbu.io.gpr
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io.instComm <> wbu.io.instComm
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io.archIntRegState <> wbu.io.archIntRegState
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io.csrState <> wbu.io.csrState
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io.trapEvt <> wbu.io.trapEvt
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io.archFpRegState <> wbu.io.archFpRegState
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io.archEvt <> wbu.io.archEvt
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}

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