style: format the code by new align rule

Author: maksyuki

rtl/tc_l2/src/main/scala/axi4/Crossbar.scala

@@ -52,7 +52,7 @@ class Crossbar extends Module with InstConfig {
   io.dxchg.ren   := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
   io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, ldAddr)
   io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
-  io.dxchg.wen   := stateReg === eumMem && io.core.sd.en
+  io.dxchg.wen   := stateReg   === eumMem   && io.core.sd.en
   io.dxchg.waddr := sdAddr
   io.dxchg.wdata := io.core.sd.data
   io.dxchg.wmask := io.core.sd.mask

rtl/tc_l2/src/main/scala/core/exec/CSRReg.scala

@@ -45,16 +45,16 @@ class CSRReg extends Module with InstConfig {
   protected val addr        = io.inst(31, 20)
   protected val mretVis     = io.inst === instMRET
   protected val ecallVis    = io.inst === instECALL
-  protected val mhartidVis  = addr === mhartidAddr
-  protected val mstatusVis  = addr === mstatusAddr
-  protected val mieVis      = addr === mieAddr
-  protected val mtvecVis    = addr === mtvecAddr
-  protected val mscratchVis = addr === mscratchAddr
-  protected val mepcVis     = addr === mepcAddr
-  protected val mcauseVis   = addr === mcauseAddr
-  protected val mipVis      = addr === mipAddr
-  protected val mcycleVis   = addr === mcycleAddr
-  protected val medelegVis  = addr === medelegAddr
+  protected val mhartidVis  = addr    === mhartidAddr
+  protected val mstatusVis  = addr    === mstatusAddr
+  protected val mieVis      = addr    === mieAddr
+  protected val mtvecVis    = addr    === mtvecAddr
+  protected val mscratchVis = addr    === mscratchAddr
+  protected val mepcVis     = addr    === mepcAddr
+  protected val mcauseVis   = addr    === mcauseAddr
+  protected val mipVis      = addr    === mipAddr
+  protected val mcycleVis   = addr    === mcycleAddr
+  protected val medelegVis  = addr    === medelegAddr
 
   protected val rdVal = MuxLookup(
     addr,

rtl/tc_l2/src/main/scala/core/exec/EXU.scala

@@ -32,8 +32,8 @@ class EXU extends Module with InstConfig {
   // handle bypass signal
   protected val bypassMemSrc1En = io.bypassMem.wen && (rs1 === io.bypassMem.wdest) && (rs1 =/= 0.U)
   protected val bypassMemSrc2En = io.bypassMem.wen && (rs2 === io.bypassMem.wdest) && (rs2 =/= 0.U)
-  protected val bypassWbSrc1En  = io.bypassWb.wen && (rs1 === io.bypassWb.wdest) && (rs1 =/= 0.U)
-  protected val bypassWbSrc2En  = io.bypassWb.wen && (rs2 === io.bypassWb.wdest) && (rs2 =/= 0.U)
+  protected val bypassWbSrc1En  = io.bypassWb.wen  && (rs1 === io.bypassWb.wdest)  && (rs1 =/= 0.U)
+  protected val bypassWbSrc2En  = io.bypassWb.wen  && (rs2 === io.bypassWb.wdest)  && (rs2 =/= 0.U)
   protected val src1            = Mux(bypassMemSrc1En, io.bypassMem.data, Mux(bypassWbSrc1En, io.bypassWb.data, exReg.src1))
   protected val src2            = Mux(bypassMemSrc2En, io.bypassMem.data, Mux(bypassWbSrc2En, io.bypassWb.data, exReg.src2))
 
@@ -82,12 +82,12 @@ class EXU extends Module with InstConfig {
 
   io.nxtPC.trap  := valid && (timeIntrEn || ecallEn)
   io.nxtPC.mtvec := csrReg.io.csrState.mtvec
-  io.nxtPC.mret  := valid && (isa === instMRET)
+  io.nxtPC.mret  := valid && (isa       === instMRET)
   io.nxtPC.mepc  := csrReg.io.csrState.mepc
   // (pred, fact)--->(NT, T) or (T, NT)
-  protected val predNTfactT = branch && !predTaken
+  protected val predNTfactT = branch  && !predTaken
   protected val predTfactNT = !branch && predTaken
-  io.nxtPC.branch := valid && (predNTfactT || predTfactNT)
+  io.nxtPC.branch := valid && (predNTfactT     || predTfactNT)
   io.nxtPC.tgt    := Mux(valid && predNTfactT, tgt, Mux(valid && predTfactNT, pc + 4.U, 0.U(XLen.W)))
   io.stall        := valid && (io.nxtPC.branch || timeIntrEn || ecallEn || (isa === instMRET))
 

rtl/tc_l2/src/main/scala/core/ma/CLINT.scala

@@ -23,7 +23,7 @@ class CLINT extends Module with InstConfig {
   // check if a mmio access
   protected val cren   = io.cld.en && (mtimecmpVis || mtimeVis) && io.valid
   protected val cwen   = io.csd.en && (mtimecmpVis || mtimeVis) && io.valid
-  protected val cvalid = cren || cwen
+  protected val cvalid = cren      || cwen
 
   // generate low speed clock
   protected val (tickCnt, cntWrap) = Counter(true.B, 5)