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Add support for new ST and LD instructions to the disassembler
The following new instructions are now supported: * LDL, LDH * STL, STH, ST32, STI32, STI, STO Note: The disassembler will return LD instead of LDL and ST instead of STL, because they are each synonyms of the other. We can only pick either and so we picked the keyword that exists across both the ESP32 and the ESP32-S2/S3.
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8 files changed

+341
-12
lines changed

8 files changed

+341
-12
lines changed

‎tests/03_disassembler_tests.sh

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,11 +13,11 @@ test_disassembling_a_file() {
1313
fi
1414

1515
testname=all_opcodes
16-
fixture=fixtures/${testname}.S
16+
fixture=fixtures/${testname}.${cpu}.S
1717
echo -e "\tBuilding $fixture using micropython-esp32-ulp ($cpu)"
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1919
log_file="${testname}.log"
20-
ulp_file="fixtures/${testname}.ulp"
20+
ulp_file="fixtures/${testname}.${cpu}.ulp"
2121
micropython -m esp32_ulp -c $cpu $fixture 1>$log_file # generates $ulp_file
2222

2323
lst_file="${testname}.$cpu.lst"

‎tests/decode_s2.py

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,8 +86,23 @@ def test_all_instructions():
8686
# OPCODE_ADC = 5
8787
assert_decode("00000050", opcodes._adc, 'ADC r0, 0, 0')
8888

89-
# OPCODE_ST = 6
89+
# OPCODE_ST = 6, SUB_OPCODE_ST
9090
assert_decode("80010068", opcodes._st, 'ST r0, r0, 0')
91+
assert_decode("c0010068", opcodes._st, 'STH r0, r0, 0')
92+
assert_decode("90000068", opcodes._st, 'STL r0, r0, 0, 1')
93+
assert_decode("d0000068", opcodes._st, 'STH r0, r0, 0, 1')
94+
assert_decode("00000068", opcodes._st, 'ST32 r0, r0, 0, 0')
95+
assert_decode("10000068", opcodes._st, 'ST32 r0, r0, 0, 1')
96+
97+
# OPCODE_ST = 6, SUB_OPCODE_ST_AUTO
98+
assert_decode("80010062", opcodes._st, 'STI r0, r0')
99+
assert_decode("90000062", opcodes._st, 'STI r0, r0, 1')
100+
assert_decode("00000062", opcodes._st, 'STI32 r0, r0, 0')
101+
assert_decode("10000062", opcodes._st, 'STI32 r0, r0, 1')
102+
103+
# OPCODE_ST = 6, SUB_OPCODE_ST_OFFSET
104+
assert_decode("00000064", opcodes._st, 'STO 0')
105+
assert_decode("00040064", opcodes._st, 'STO 1')
91106

92107
# OPCODE_ALU = 7, SUB_OPCODE_ALU_REG
93108
assert_decode("00000070", opcodes._alu_reg, 'ADD r0, r0, r0')

‎tests/fixtures/all_opcodes-v.esp32s2.lst

Lines changed: 182 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
header
22
ULP magic : b'ulp\x00' (0x00706c75)
33
.text offset : 12 (0x0c)
4-
.text size : 176 (0xb0)
5-
.data offset : 188 (0xbc)
4+
.text size : 244 (0xf4)
5+
.data offset : 256 (0x100)
66
.data size : 8 (0x08)
77
.bss size : 0 (0x00)
88
----------------------------------------
@@ -63,6 +63,9 @@ ULP magic : b'ulp\x00' (0x00706c75)
6363
sub_opcode = 4
6464
unused1 = 0
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unused2 = 0
66+
label = 0
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upper = 0
68+
wr_way = 3
6669
0020 06000070 ADD r2, r1, r0
6770
dreg = 2
6871
opcode = 7
@@ -349,7 +352,182 @@ ULP magic : b'ulp\x00' (0x00706c75)
349352
sreg = 1
350353
unused1 = 0
351354
unused2 = 0
355+
rd_upper = 0
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00b0 00000040 NOP
357+
cycles = 0
358+
opcode = 4
359+
unused = 0
360+
00b4 092000d0 LD r1, r2, 8
361+
dreg = 1
362+
offset = 8
363+
opcode = 13 (0x0d)
364+
sreg = 2
365+
unused1 = 0
366+
unused2 = 0
367+
rd_upper = 0
368+
00b8 092000d8 LDH r1, r2, 8
369+
dreg = 1
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offset = 8
371+
opcode = 13 (0x0d)
372+
sreg = 2
373+
unused1 = 0
374+
unused2 = 0
375+
rd_upper = 1
376+
00bc 89210068 ST r1, r2, 8
377+
dreg = 2
378+
offset = 8
379+
opcode = 6
380+
sreg = 1
381+
sub_opcode = 4
382+
unused1 = 0
383+
unused2 = 0
384+
label = 0
385+
upper = 0
386+
wr_way = 3
387+
00c0 89210068 ST r1, r2, 8
388+
dreg = 2
389+
offset = 8
390+
opcode = 6
391+
sreg = 1
392+
sub_opcode = 4
393+
unused1 = 0
394+
unused2 = 0
395+
label = 0
396+
upper = 0
397+
wr_way = 3
398+
00c4 99200068 STL r1, r2, 8, 1
399+
dreg = 2
400+
offset = 8
401+
opcode = 6
402+
sreg = 1
403+
sub_opcode = 4
404+
unused1 = 0
405+
unused2 = 0
406+
label = 1
407+
upper = 0
408+
wr_way = 1
409+
00c8 c9210068 STH r1, r2, 8
410+
dreg = 2
411+
offset = 8
412+
opcode = 6
413+
sreg = 1
414+
sub_opcode = 4
415+
unused1 = 0
416+
unused2 = 0
417+
label = 0
418+
upper = 1
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wr_way = 3
420+
00cc c9210068 STH r1, r2, 8
421+
dreg = 2
422+
offset = 8
423+
opcode = 6
424+
sreg = 1
425+
sub_opcode = 4
426+
unused1 = 0
427+
unused2 = 0
428+
label = 0
429+
upper = 1
430+
wr_way = 3
431+
00d0 d9200068 STH r1, r2, 8, 1
432+
dreg = 2
433+
offset = 8
434+
opcode = 6
435+
sreg = 1
436+
sub_opcode = 4
437+
unused1 = 0
438+
unused2 = 0
439+
label = 1
440+
upper = 1
441+
wr_way = 1
442+
00d4 09200068 ST32 r1, r2, 8, 0
443+
dreg = 2
444+
offset = 8
445+
opcode = 6
446+
sreg = 1
447+
sub_opcode = 4
448+
unused1 = 0
449+
unused2 = 0
450+
label = 0
451+
upper = 0
452+
wr_way = 0
453+
00d8 19200068 ST32 r1, r2, 8, 1
454+
dreg = 2
455+
offset = 8
456+
opcode = 6
457+
sreg = 1
458+
sub_opcode = 4
459+
unused1 = 0
460+
unused2 = 0
461+
label = 1
462+
upper = 0
463+
wr_way = 0
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00dc 89010062 STI r1, r2
465+
dreg = 2
466+
offset = 0
467+
opcode = 6
468+
sreg = 1
469+
sub_opcode = 1
470+
unused1 = 0
471+
unused2 = 0
472+
label = 0
473+
upper = 0
474+
wr_way = 3
475+
00e0 89010062 STI r1, r2
476+
dreg = 2
477+
offset = 0
478+
opcode = 6
479+
sreg = 1
480+
sub_opcode = 1
481+
unused1 = 0
482+
unused2 = 0
483+
label = 0
484+
upper = 0
485+
wr_way = 3
486+
00e4 99000062 STI r1, r2, 1
487+
dreg = 2
488+
offset = 0
489+
opcode = 6
490+
sreg = 1
491+
sub_opcode = 1
492+
unused1 = 0
493+
unused2 = 0
494+
label = 1
495+
upper = 0
496+
wr_way = 1
497+
00e8 09000062 STI32 r1, r2, 0
498+
dreg = 2
499+
offset = 0
500+
opcode = 6
501+
sreg = 1
502+
sub_opcode = 1
503+
unused1 = 0
504+
unused2 = 0
505+
label = 0
506+
upper = 0
507+
wr_way = 0
508+
00ec 19000062 STI32 r1, r2, 1
509+
dreg = 2
510+
offset = 0
511+
opcode = 6
512+
sreg = 1
513+
sub_opcode = 1
514+
unused1 = 0
515+
unused2 = 0
516+
label = 1
517+
upper = 0
518+
wr_way = 0
519+
00f0 00200064 STO 8
520+
dreg = 0
521+
offset = 8
522+
opcode = 6
523+
sreg = 0
524+
sub_opcode = 2
525+
unused1 = 0
526+
unused2 = 0
527+
label = 0
528+
upper = 0
529+
wr_way = 0
352530
----------------------------------------
353531
.data
354-
00b0 00000000 <empty>
355-
00b4 fecadec0 <non-empty>
532+
00f4 00000000 <empty>
533+
00f8 fecadec0 <non-empty>

‎tests/fixtures/all_opcodes.S renamed to ‎tests/fixtures/all_opcodes.esp32.S

File renamed without changes.

‎tests/fixtures/all_opcodes.esp32s2.S

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
1+
.data
2+
empty: .long 0
3+
magic: .long 0xc0decafe
4+
5+
.text
6+
REG_WR 0x123, 1, 2, 3
7+
8+
REG_RD 0x321, 2, 1
9+
10+
I2C_RD 3, 2, 1, 0
11+
I2C_WR 0, 1, 2, 3, 4
12+
13+
NOP
14+
WAIT 7
15+
16+
ADC r3, 2, 1
17+
18+
ST r3, r2, 1
19+
20+
ADD r2, r1, r0
21+
SUB r2, r1, r0
22+
AND r2, r1, r0
23+
OR r2, r1, r0
24+
MOVE r2, r1
25+
LSH r2, r1, r0
26+
RSH r2, r1, r0
27+
28+
ADD r2, r1, 0
29+
SUB r2, r1, 0
30+
AND r2, r1, 0
31+
OR r2, r1, 0
32+
MOVE r1, 0
33+
LSH r2, r1, 0
34+
RSH r2, r1, 0
35+
36+
STAGE_RST
37+
STAGE_INC 7
38+
STAGE_DEC 3
39+
40+
JUMP r0
41+
JUMP r1, EQ
42+
JUMP r2, OV
43+
44+
JUMP 0
45+
JUMP 0, EQ
46+
JUMP 0, OV
47+
48+
JUMPR 0, 1, LT
49+
JUMPR 4, 5, GT
50+
JUMPR 8, 7, EQ
51+
52+
JUMPS 0, 1, LT
53+
JUMPS 4, 5, GT
54+
JUMPS 8, 7, EQ
55+
JUMPS 12, 9, LE
56+
JUMPS 16, 11, GE
57+
58+
WAKE
59+
SLEEP 7
60+
61+
TSENS r1, 2
62+
63+
HALT
64+
65+
LD r2, r1, 0
66+
67+
# ESP32-S2 specific instructions
68+
NOP # marker
69+
70+
LDL R1, R2, 0x20
71+
LDH R1, R2, 0x20
72+
73+
STL R1, R2, 0x20
74+
STL R1, R2, 0x20, 0
75+
STL R1, R2, 0x20, 1
76+
77+
STH R1, R2, 0x20
78+
STH R1, R2, 0x20, 0
79+
STH R1, R2, 0x20, 1
80+
81+
ST32 R1, R2, 0x20, 0
82+
ST32 R1, R2, 0x20, 1
83+
84+
STI R1, R2
85+
STI R1, R2, 0
86+
STI R1, R2, 1
87+
88+
STI32 R1, R2, 0
89+
STI32 R1, R2, 1
90+
91+
STO 0x20

‎tests/fixtures/all_opcodes.esp32s2.lst

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,23 @@
4343
00a4 090000a0 TSENS r1, 2
4444
00a8 000000b0 HALT
4545
00ac 060000d0 LD r2, r1, 0
46+
00b0 00000040 NOP
47+
00b4 092000d0 LD r1, r2, 8
48+
00b8 092000d8 LDH r1, r2, 8
49+
00bc 89210068 ST r1, r2, 8
50+
00c0 89210068 ST r1, r2, 8
51+
00c4 99200068 STL r1, r2, 8, 1
52+
00c8 c9210068 STH r1, r2, 8
53+
00cc c9210068 STH r1, r2, 8
54+
00d0 d9200068 STH r1, r2, 8, 1
55+
00d4 09200068 ST32 r1, r2, 8, 0
56+
00d8 19200068 ST32 r1, r2, 8, 1
57+
00dc 89010062 STI r1, r2
58+
00e0 89010062 STI r1, r2
59+
00e4 99000062 STI r1, r2, 1
60+
00e8 09000062 STI32 r1, r2, 0
61+
00ec 19000062 STI32 r1, r2, 1
62+
00f0 00200064 STO 8
4663
.data
47-
00b0 00000000 <empty>
48-
00b4 fecadec0 <non-empty>
64+
00f4 00000000 <empty>
65+
00f8 fecadec0 <non-empty>

‎tests/fixtures/manual_bytes-v.esp32s2.lst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,9 @@
1515
sub_opcode = 4
1616
unused1 = 0
1717
unused2 = 0
18+
label = 0
19+
upper = 0
20+
wr_way = 3
1821
0008 2705cc19 REG_WR 0x127, 19, 19, 1
1922
addr = 39 (0x27)
2023
data = 1

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