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| 1 | +/** |
| 2 | + ****************************************************************************** |
| 3 | + * @file stm32n6xx.h |
| 4 | + * @author MCD Application Team |
| 5 | + * @brief CMSIS STM32N6xx Device Peripheral Access Layer Header File. |
| 6 | + * |
| 7 | + * The file is the unique include file that the application programmer |
| 8 | + * is using in the C source code, usually in main.c. This file contains: |
| 9 | + * - Configuration section that allows to select: |
| 10 | + * - The STM32N6xx device used in the target application |
| 11 | + * |
| 12 | + ****************************************************************************** |
| 13 | + * @attention |
| 14 | + * |
| 15 | + * Copyright (c) 2023 STMicroelectronics. |
| 16 | + * All rights reserved. |
| 17 | + * |
| 18 | + * This software is licensed under terms that can be found in the LICENSE file |
| 19 | + * in the root directory of this software component. |
| 20 | + * If no LICENSE file comes with this software, it is provided AS-IS. |
| 21 | + * |
| 22 | + ****************************************************************************** |
| 23 | + */ |
| 24 | + |
| 25 | +/** @addtogroup CMSIS |
| 26 | + * @{ |
| 27 | + */ |
| 28 | + |
| 29 | +/** @addtogroup STM32N6xx |
| 30 | + * @{ |
| 31 | + */ |
| 32 | + |
| 33 | +#ifndef STM32N6xx_H |
| 34 | +#define STM32N6xx_H |
| 35 | + |
| 36 | +#ifdef __cplusplus |
| 37 | +extern "C" { |
| 38 | +#endif /* __cplusplus */ |
| 39 | + |
| 40 | +/** @addtogroup Library_configuration_section |
| 41 | + * @{ |
| 42 | + */ |
| 43 | + |
| 44 | +/** |
| 45 | + * @brief STM32 Family |
| 46 | + */ |
| 47 | +#if !defined (STM32N6) |
| 48 | +#define STM32N6 |
| 49 | +#endif /* STM32N6 */ |
| 50 | + |
| 51 | +/* Uncomment the line below according to the target STM32N6 device used in your |
| 52 | + application |
| 53 | + */ |
| 54 | + |
| 55 | +#if !defined (STM32N647xx) && !defined (STM32N657xx) |
| 56 | + /* #define STM32N647xx */ /*!< STM32N647xx Devices */ |
| 57 | + /* #define STM32N657xx */ /*!< STM32N657xx Devices */ |
| 58 | +#endif |
| 59 | + |
| 60 | +/* Tip: To avoid modifying this file each time you need to switch between these |
| 61 | + devices, you can define the device in your toolchain compiler preprocessor. |
| 62 | + */ |
| 63 | + |
| 64 | +/** |
| 65 | + * @brief CMSIS Device version number |
| 66 | + */ |
| 67 | +#define __STM32N6_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ |
| 68 | +#define __STM32N6_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ |
| 69 | +#define __STM32N6_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ |
| 70 | +#define __STM32N6_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ |
| 71 | +#define __STM32N6_CMSIS_VERSION ((__STM32N6_CMSIS_VERSION_MAIN << 24U)\ |
| 72 | + |(__STM32N6_CMSIS_VERSION_SUB1 << 16U)\ |
| 73 | + |(__STM32N6_CMSIS_VERSION_SUB2 << 8U )\ |
| 74 | + |(__STM32N6_CMSIS_VERSION_RC)) |
| 75 | + |
| 76 | +/** |
| 77 | + * @} |
| 78 | + */ |
| 79 | + |
| 80 | +/** @addtogroup Device_Included |
| 81 | + * @{ |
| 82 | + */ |
| 83 | + |
| 84 | +#if defined(STM32N657xx) |
| 85 | + #include "stm32n657xx.h" |
| 86 | +#elif defined(STM32N655xx) |
| 87 | + #include "stm32n655xx.h" |
| 88 | +#elif defined(STM32N647xx) |
| 89 | + #include "stm32n647xx.h" |
| 90 | +#elif defined(STM32N645xx) |
| 91 | + #include "stm32n645xx.h" |
| 92 | +#else |
| 93 | + #error "Please select first the target STM32N6xx device used in your application (in stm32n6xx.h file)" |
| 94 | +#endif |
| 95 | + |
| 96 | +/** |
| 97 | + * @} |
| 98 | + */ |
| 99 | + |
| 100 | +/** @addtogroup Exported_types |
| 101 | + * @{ |
| 102 | + */ |
| 103 | +typedef enum |
| 104 | +{ |
| 105 | + RESET = 0, |
| 106 | + SET = !RESET |
| 107 | +} FlagStatus, ITStatus; |
| 108 | + |
| 109 | +typedef enum |
| 110 | +{ |
| 111 | + DISABLE = 0, |
| 112 | + ENABLE = !DISABLE |
| 113 | +} FunctionalState; |
| 114 | +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
| 115 | + |
| 116 | +typedef enum |
| 117 | +{ |
| 118 | + SUCCESS = 0, |
| 119 | + ERROR = !SUCCESS |
| 120 | +} ErrorStatus; |
| 121 | + |
| 122 | +/** |
| 123 | + * @} |
| 124 | + */ |
| 125 | + |
| 126 | + |
| 127 | +/** @addtogroup Exported_macros |
| 128 | + * @{ |
| 129 | + */ |
| 130 | +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
| 131 | + |
| 132 | +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
| 133 | + |
| 134 | +#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
| 135 | + |
| 136 | +#define CLEAR_REG(REG) ((REG) = (0x0)) |
| 137 | + |
| 138 | +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
| 139 | + |
| 140 | +#define READ_REG(REG) ((REG)) |
| 141 | + |
| 142 | +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
| 143 | + |
| 144 | +/* Use of CMSIS compiler intrinsics for register exclusive access */ |
| 145 | +/* Atomic 32-bit register access macro to set one or several bits */ |
| 146 | +#define ATOMIC_SET_BIT(REG, BIT) \ |
| 147 | + do { \ |
| 148 | + uint32_t val; \ |
| 149 | + do { \ |
| 150 | + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ |
| 151 | + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ |
| 152 | + } while(0) |
| 153 | + |
| 154 | +/* Atomic 32-bit register access macro to clear one or several bits */ |
| 155 | +#define ATOMIC_CLEAR_BIT(REG, BIT) \ |
| 156 | + do { \ |
| 157 | + uint32_t val; \ |
| 158 | + do { \ |
| 159 | + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ |
| 160 | + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ |
| 161 | + } while(0) |
| 162 | + |
| 163 | +/* Atomic 32-bit register access macro to clear and set one or several bits */ |
| 164 | +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ |
| 165 | + do { \ |
| 166 | + uint32_t val; \ |
| 167 | + do { \ |
| 168 | + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ |
| 169 | + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ |
| 170 | + } while(0) |
| 171 | + |
| 172 | +/* Atomic 16-bit register access macro to set one or several bits */ |
| 173 | +#define ATOMIC_SETH_BIT(REG, BIT) \ |
| 174 | + do { \ |
| 175 | + uint16_t val; \ |
| 176 | + do { \ |
| 177 | + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ |
| 178 | + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ |
| 179 | + } while(0) |
| 180 | + |
| 181 | +/* Atomic 16-bit register access macro to clear one or several bits */ |
| 182 | +#define ATOMIC_CLEARH_BIT(REG, BIT) \ |
| 183 | + do { \ |
| 184 | + uint16_t val; \ |
| 185 | + do { \ |
| 186 | + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ |
| 187 | + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ |
| 188 | + } while(0) |
| 189 | + |
| 190 | +/* Atomic 16-bit register access macro to clear and set one or several bits */ |
| 191 | +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ |
| 192 | + do { \ |
| 193 | + uint16_t val; \ |
| 194 | + do { \ |
| 195 | + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ |
| 196 | + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ |
| 197 | + } while(0) |
| 198 | + |
| 199 | +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) |
| 200 | + |
| 201 | +/** |
| 202 | + * @} |
| 203 | + */ |
| 204 | + |
| 205 | +#if defined (USE_HAL_DRIVER) |
| 206 | + #include "stm32n6xx_hal.h" |
| 207 | +#endif /* USE_HAL_DRIVER */ |
| 208 | + |
| 209 | +#ifdef __cplusplus |
| 210 | +} |
| 211 | +#endif /* __cplusplus */ |
| 212 | + |
| 213 | +#endif /* STM32N6xx_H */ |
| 214 | + |
| 215 | +/** |
| 216 | + * @} |
| 217 | + */ |
| 218 | + |
| 219 | +/** |
| 220 | + * @} |
| 221 | + */ |
| 222 | + |
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