Users/nmalkapuram/updatelscpu parser logic (#176)

* Adding logic for lscpu parser update

* Updating lscpu parser and adding unittests

* Resolving comments

* fixing double.NaN values

Author: nmalkapuram

src/VirtualClient/VirtualClient.Contracts.UnitTests/Examples/lscpu/lscpu_results3.txt renamed to src/VirtualClient/VirtualClient.Contracts.UnitTests/Examples/lscpu/lscpu_results_intel_3.txt

@@ -0,0 +1,48 @@
+Architecture:            x86_64
+  CPU op-mode(s):        32-bit, 64-bit
+  Address sizes:         46 bits physical, 57 bits virtual
+  Byte Order:            Little Endian
+CPU(s):                  28
+  On-line CPU(s) list:   0-27
+Vendor ID:               GenuineIntel
+  Model name:            Intel(R) Xeon(R) Platinum 8480C
+    CPU family:          6
+    Model:               143
+    Thread(s) per core:  2
+    Core(s) per socket:  7
+    Socket(s):           2
+    Stepping:            8
+    CPU max MHz:         380.0000
+    CPU min MHz:         80.0000
+    BogoMIPS:            4000.00
+    Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon
+                         ebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4
+                          x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ib
+                          stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflu
+                         opt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoin
+                          dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq
+                         a57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabiliti
+Virtualization features:
+  Virtualization:        VT-x
+Caches (sum of all):
+  L1d:                   4.3 MiB (112 instances)
+  L1i:                   2.5 MiB (112 instances)
+  L2:                    24 MiB (112 instances)
+  L3:                    20 MiB (2 instances)
+NUMA:
+  NUMA node(s):          2
+  NUMA node0 CPU(s):     0-5,18-23
+  NUMA node1 CPU(s):     6-17,24-27
+Vulnerabilities:
+  Gather data sampling:  Not affected
+  Itlb multihit:         Not affected
+  L1tf:                  Not affected
+  Mds:                   Not affected
+  Meltdown:              Not affected
+  Mmio stale data:       Not affected
+  Retbleed:              Not affected
+  Spec store bypass:     Mitigation; Speculative Store Bypass disabled via prctl
+  Spectre v1:            Mitigation; usercopy/swapgs barriers and __user pointer sanitization
+  Spectre v2:            Mitigation; Enhanced IBRS, IBPB conditional, RSB filling, PBRSB-eIBRS SW sequence
+  Srbds:                 Not affected
+  Tsx async abort:       Not affected

src/VirtualClient/VirtualClient.Contracts.UnitTests/Examples/lscpu/lscpu_results_intel_4.txt

@@ -28,6 +28,18 @@ public void LscpuParserParsesTheExpectedResultsFromIntelSystems_Scenario1()
             Assert.AreEqual(1, info.SocketCount);
             Assert.AreEqual(1, info.NumaNodeCount);
             Assert.IsTrue(info.IsHyperthreadingEnabled);
+            Assert.AreEqual(double.NaN, info.MaxFrequencyMHz);
+            Assert.AreEqual(double.NaN, info.MinFrequencyMHz);
+            Assert.AreEqual(2793.438, info.FrequencyMHz);
+
+            Assert.AreEqual(7, info.Flags.Count);
+            Assert.AreEqual("x86_64", info.Flags["Architecture"]);
+            Assert.AreEqual("32-bit, 64-bit", info.Flags["CPU op-mode(s)"]);
+            Assert.AreEqual("46 bits physical, 48 bits virtual", info.Flags["Address sizes"]);
+            Assert.AreEqual("Little Endian", info.Flags["Byte Order"]);
+            Assert.AreEqual("0-3", info.Flags["NUMA node0 CPU(s)"]);
+            Assert.AreEqual("0-3", info.Flags["On-line CPU(s) list"]);
+            Assert.AreEqual("5586.87", info.Flags["BogoMIPS"]);
 
             IConvertible cacheMemory = 0;
             Assert.IsNotEmpty(info.Caches);
@@ -55,6 +67,18 @@ public void LscpuParserParsesTheExpectedResultsFromIntelSystems_Scenario2()
             Assert.AreEqual(1, info.SocketCount);
             Assert.AreEqual(1, info.NumaNodeCount);
             Assert.IsFalse(info.IsHyperthreadingEnabled);
+            Assert.AreEqual(double.NaN, info.MaxFrequencyMHz);
+            Assert.AreEqual(double.NaN, info.MinFrequencyMHz);
+            Assert.AreEqual(2793.438, info.FrequencyMHz);
+
+            Assert.AreEqual(7, info.Flags.Count);
+            Assert.AreEqual("x86_64", info.Flags["Architecture"]);
+            Assert.AreEqual("32-bit, 64-bit", info.Flags["CPU op-mode(s)"]);
+            Assert.AreEqual("46 bits physical, 48 bits virtual", info.Flags["Address sizes"]);
+            Assert.AreEqual("Little Endian", info.Flags["Byte Order"]);
+            Assert.AreEqual("0-3", info.Flags["NUMA node0 CPU(s)"]);
+            Assert.AreEqual("0-3", info.Flags["On-line CPU(s) list"]);
+            Assert.AreEqual("5586.87", info.Flags["BogoMIPS"]);
 
             IConvertible cacheMemory = 0;
             Assert.IsNotEmpty(info.Caches);
@@ -82,6 +106,17 @@ public void LscpuParserParsesTheExpectedResultsFromAmpereSystems_Scenario1()
             Assert.AreEqual(1, info.SocketCount);
             Assert.AreEqual(1, info.NumaNodeCount);
             Assert.IsFalse(info.IsHyperthreadingEnabled);
+            Assert.AreEqual(double.NaN, info.MaxFrequencyMHz);
+            Assert.AreEqual(double.NaN, info.MinFrequencyMHz);
+            Assert.AreEqual(double.NaN, info.FrequencyMHz);
+
+            Assert.AreEqual(6, info.Flags.Count);
+            Assert.AreEqual("aarch64", info.Flags["Architecture"]);
+            Assert.AreEqual("32-bit, 64-bit", info.Flags["CPU op-mode(s)"]);
+            Assert.AreEqual("Little Endian", info.Flags["Byte Order"]);
+            Assert.AreEqual("0,1", info.Flags["NUMA node0 CPU(s)"]);
+            Assert.AreEqual("0,1", info.Flags["On-line CPU(s) list"]);
+            Assert.AreEqual("50", info.Flags["BogoMIPS"]);
 
             IConvertible cacheMemory = 0;
             Assert.IsNotEmpty(info.Caches);
@@ -97,7 +132,7 @@ public void LscpuParserParsesTheExpectedResultsFromAmpereSystems_Scenario1()
         [Test]
         public void LscpuParserParsesTheExpectedResultsFromAWSSystems_Scenario3()
         {
-            string results = File.ReadAllText(Path.Combine(MockFixture.ExamplesDirectory, "lscpu", "lscpu_results3.txt"));
+            string results = File.ReadAllText(Path.Combine(MockFixture.ExamplesDirectory, "lscpu", "lscpu_results_intel_3.txt"));
             LscpuParser parser = new LscpuParser(results);
             CpuInfo info = parser.Parse();
 
@@ -109,6 +144,67 @@ public void LscpuParserParsesTheExpectedResultsFromAWSSystems_Scenario3()
             Assert.AreEqual(1, info.SocketCount);
             Assert.AreEqual(1, info.NumaNodeCount);
             Assert.IsFalse(info.IsHyperthreadingEnabled);
+            Assert.AreEqual(double.NaN, info.MaxFrequencyMHz);
+            Assert.AreEqual(double.NaN, info.MinFrequencyMHz);
+            Assert.AreEqual(double.NaN, info.FrequencyMHz);
+
+            Assert.AreEqual(6, info.Flags.Count);
+            Assert.AreEqual("aarch64", info.Flags["Architecture"]);
+            Assert.AreEqual("32-bit, 64-bit", info.Flags["CPU op-mode(s)"]);
+            Assert.AreEqual("Little Endian", info.Flags["Byte Order"]);
+            Assert.AreEqual("0,1", info.Flags["NUMA node0 CPU(s)"]);
+            Assert.AreEqual("0,1", info.Flags["On-line CPU(s) list"]);
+            Assert.AreEqual("2100", info.Flags["BogoMIPS"]);
+
+            IConvertible cacheMemory = 0;
+            Assert.IsNotEmpty(info.Caches);
+
+            Assert.IsTrue(info.Caches.Count() == 5);
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L1" && cache.SizeInBytes == 262144));
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L1d" && cache.SizeInBytes == 131072));
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L1i" && cache.SizeInBytes == 131072));
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L2" && cache.SizeInBytes == 2097152));
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L3" && cache.SizeInBytes == 33554432));
+        }
+
+        [Test]
+        public void LscpuParserParsesTheExpectedResultsIntelLabSystems_Scenario4()
+        {
+            string results = File.ReadAllText(Path.Combine(MockFixture.ExamplesDirectory, "lscpu", "lscpu_results_intel_4.txt"));
+            LscpuParser parser = new LscpuParser(results);
+            CpuInfo info = parser.Parse();
+
+            Assert.IsNotNull(info);
+            Assert.AreEqual("Intel(R) Xeon(R) Platinum 8480C", info.Name);
+            Assert.AreEqual("Intel(R) Xeon(R) Platinum 8480C Family 6 Model 143 Stepping 8, GenuineIntel", info.Description);
+            Assert.AreEqual(28, info.LogicalCoreCount);
+            Assert.AreEqual(14, info.PhysicalCoreCount);
+            Assert.AreEqual(2, info.SocketCount);
+            Assert.AreEqual(2, info.NumaNodeCount);
+            Assert.IsTrue(info.IsHyperthreadingEnabled);
+            Assert.AreEqual(380, info.MaxFrequencyMHz);
+            Assert.AreEqual(80, info.MinFrequencyMHz);
+            Assert.AreEqual(double.NaN, info.FrequencyMHz);
+
+            Assert.AreEqual(8, info.Flags.Count);
+            Assert.AreEqual("x86_64", info.Flags["Architecture"]);
+            Assert.AreEqual("32-bit, 64-bit", info.Flags["CPU op-mode(s)"]);
+            Assert.AreEqual("46 bits physical, 57 bits virtual", info.Flags["Address sizes"]);
+            Assert.AreEqual("Little Endian", info.Flags["Byte Order"]);
+            Assert.AreEqual("0-5,18-23", info.Flags["NUMA node0 CPU(s)"]);
+            Assert.AreEqual("6-17,24-27", info.Flags["NUMA node1 CPU(s)"]);
+            Assert.AreEqual("0-27", info.Flags["On-line CPU(s) list"]);
+            Assert.AreEqual("4000", info.Flags["BogoMIPS"]);
+
+            IConvertible cacheMemory = 0;
+            Assert.IsNotEmpty(info.Caches);
+
+            Assert.IsTrue(info.Caches.Count() == 5);
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L1" && cache.SizeInBytes == 7130316));
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L1d" && cache.SizeInBytes == 4508876));
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L1i" && cache.SizeInBytes == 2621440));
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L2" && cache.SizeInBytes == 25165824));
+            Assert.IsTrue(info.Caches.Any(cache => cache.Name == "L3" && cache.SizeInBytes == 20971520));
         }
     }
 }

src/VirtualClient/VirtualClient.Contracts.UnitTests/Parser/LscpuParserTests.cs

@@ -23,7 +23,11 @@ public class CpuInfo
         /// <param name="numaNodeCount">The number of NUMA nodes on the system.</param>
         /// <param name="hyperThreadingEnabled">True/false whether CPU hyperthreading is enabled on the system.</param>
         /// <param name="caches">Memory caches for the CPU (e.g. L1, L2, L3).</param>
-        public CpuInfo(string name, string description, int physicalCoreCount, int logicalCoreCount, int socketCount, int numaNodeCount, bool hyperThreadingEnabled, IEnumerable<CpuCacheInfo> caches = null)
+        /// <param name="flags">List of other information about CPU</param>
+        /// <param name="maxFrequency">Maximum CPU frequency in MHz.</param>
+        /// <param name="minFrequency">Minimum CPU frequency in MHz.</param>
+        /// <param name="frequency">Currrent frequency of CPU in MHz.</param>
+        public CpuInfo(string name, string description, int physicalCoreCount, int logicalCoreCount, int socketCount, int numaNodeCount, bool hyperThreadingEnabled, IEnumerable<CpuCacheInfo> caches = null,  Dictionary<string, string> flags = null, double maxFrequency = double.NaN, double minFrequency = double.NaN, double frequency = double.NaN)
             : base()
         {
             name.ThrowIfNull(nameof(name));
@@ -44,6 +48,26 @@ public CpuInfo(string name, string description, int physicalCoreCount, int logic
             {
                 this.Caches = new List<CpuCacheInfo>(caches);
             }
+
+            if (flags != null)
+            {
+                this.Flags = flags;
+            }
+
+            if (!double.IsNaN(maxFrequency))
+            {
+                this.MaxFrequencyMHz = maxFrequency;
+            }
+
+            if (!double.IsNaN(minFrequency))
+            {
+                this.MinFrequencyMHz = minFrequency;
+            }
+
+            if (!double.IsNaN(frequency))
+            {
+                this.FrequencyMHz = frequency;
+            }
         }
 
         /// <summary>
@@ -85,5 +109,25 @@ public CpuInfo(string name, string description, int physicalCoreCount, int logic
         /// The number of CPU sockets on the system.
         /// </summary>
         public int SocketCount { get; }
+
+        /// <summary>
+        /// Dictionary of other information about CPU.
+        /// </summary>
+        public Dictionary<string, string> Flags { get; }
+
+        /// <summary>
+        /// Maximum CPU frequency in MHz.
+        /// </summary>
+        public double MaxFrequencyMHz { get; set; } = double.NaN;
+
+        /// <summary>
+        /// Minimum CPU frequency in MHz.
+        /// </summary>
+        public double MinFrequencyMHz { get; set; } = double.NaN;
+
+        /// <summary>
+        /// Currrent frequency of CPU in MHz.
+        /// </summary>
+        public double FrequencyMHz { get; set; } = double.NaN;
     }
 }