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Merge tag 'rolling-lts/wsl/5.15.153.1' into linux-msft-wsl-5.15.y
Linux rolling-lts/wsl/5.15.153.1 Signed-off-by: Kelsey Steele <[email protected]>
2 parents 35bc6f3 + 97e4559 commit 33cad98

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‎Documentation/admin-guide/kernel-parameters.txt‎

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1084,8 +1084,12 @@
10841084
nopku [X86] Disable Memory Protection Keys CPU feature found
10851085
in some Intel CPUs.
10861086

1087-
<module>.async_probe [KNL]
1088-
Enable asynchronous probe on this module.
1087+
<module>.async_probe[=<bool>] [KNL]
1088+
If no <bool> value is specified or if the value
1089+
specified is not a valid <bool>, enable asynchronous
1090+
probe on this module. Otherwise, enable/disable
1091+
asynchronous probe on this module as indicated by the
1092+
<bool> value. See also: module.async_probe
10891093

10901094
early_ioremap_debug [KNL]
10911095
Enable debug messages in early_ioremap support. This
@@ -3137,6 +3141,15 @@
31373141
For details see:
31383142
Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst
31393143

3144+
module.async_probe=<bool>
3145+
[KNL] When set to true, modules will use async probing
3146+
by default. To enable/disable async probing for a
3147+
specific module, use the module specific control that
3148+
is documented under <module>.async_probe. When both
3149+
module.async_probe and <module>.async_probe are
3150+
specified, <module>.async_probe takes precedence for
3151+
the specific module.
3152+
31403153
module.sig_enforce
31413154
[KNL] When CONFIG_MODULE_SIG is set, this means that
31423155
modules without (valid) signatures will fail to load.

‎MSFT-Merge/log‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ Name SHA1
33
config/wsl 11875ba6b6b9e13b4b876035daec5dd6eeb6e6c0
44
feature/arm64-hyperv-hypercall-interface/5.15 3e314b48254cb9c3eeac699356ac605193b4b6fa
55
feature/arm64-hyperv-synthetic-clocks-timers/5.15 59db35e760b9bacc8596a3660a12420f1fa5318f
6-
feature/dxgkrnl/5.15 e8c50f197b62b147dbc3e3ee083dd1fbb66eaeaf
6+
feature/dxgkrnl/5.15 b12445891c254e843cd1cc01265ea047bf7ee300
77
feature/hvlite_virtio_pmem/5.15 9194f84de8a58bc1a83125054286d649e35054be
88
feature/page-reporting/5.15 ad427234defd6cdfdc0c21ca5b64ef589b82a421
99
feature/vpci/5.15 92c970cf37ef2b7d159905ca9df9e25f86618248
@@ -12,3 +12,4 @@ fix/vsock/5.15 c9e883dfbd7be1194e53133d888b4
1212
fix/hv_utils_clock/5.15 ef0917a0635d92d4f4fb29d8a3efdf53d38f25e6
1313
product/wsl/readme/5.15 0e1ddcfdc9986e1bf420a3663011abd79752c642
1414
product/wsl/security/5.15 ab2488a9f10a3b83b958103c9b3ed728eb57c564
15+
user/kms/5.15-D3DKMTEnumProcesses b12445891c254e843cd1cc01265ea047bf7ee300

‎Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# SPDX-License-Identifier: GPL-2.0
22
VERSION = 5
33
PATCHLEVEL = 15
4-
SUBLEVEL = 150
4+
SUBLEVEL = 153
55
EXTRAVERSION = .1
66
NAME = Trick or Treat
77

‎arch/arm/boot/dts/arm-realview-pb1176.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -435,7 +435,7 @@
435435

436436
/* Direct-mapped development chip ROM */
437437
pb1176_rom@10200000 {
438-
compatible = "direct-mapped";
438+
compatible = "mtd-rom";
439439
reg = <0x10200000 0x4000>;
440440
bank-width = <1>;
441441
};

‎arch/arm/boot/dts/imx6dl-yapp4-common.dtsi‎

Lines changed: 17 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -105,8 +105,6 @@
105105
pinctrl-names = "default";
106106
pinctrl-0 = <&pinctrl_enet>;
107107
phy-mode = "rgmii-id";
108-
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
109-
phy-reset-duration = <20>;
110108
phy-supply = <&sw2_reg>;
111109
status = "okay";
112110

@@ -119,17 +117,10 @@
119117
#address-cells = <1>;
120118
#size-cells = <0>;
121119

122-
phy_port2: phy@1 {
123-
reg = <1>;
124-
};
125-
126-
phy_port3: phy@2 {
127-
reg = <2>;
128-
};
129-
130120
switch@10 {
131121
compatible = "qca,qca8334";
132-
reg = <10>;
122+
reg = <0x10>;
123+
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
133124

134125
switch_ports: ports {
135126
#address-cells = <1>;
@@ -150,15 +141,30 @@
150141
eth2: port@2 {
151142
reg = <2>;
152143
label = "eth2";
144+
phy-mode = "internal";
153145
phy-handle = <&phy_port2>;
154146
};
155147

156148
eth1: port@3 {
157149
reg = <3>;
158150
label = "eth1";
151+
phy-mode = "internal";
159152
phy-handle = <&phy_port3>;
160153
};
161154
};
155+
156+
mdio {
157+
#address-cells = <1>;
158+
#size-cells = <0>;
159+
160+
phy_port2: ethernet-phy@1 {
161+
reg = <1>;
162+
};
163+
164+
phy_port3: ethernet-phy@2 {
165+
reg = <2>;
166+
};
167+
};
162168
};
163169
};
164170
};

‎arch/arm/crypto/sha256_glue.c‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -24,32 +24,29 @@
2424

2525
#include "sha256_glue.h"
2626

27-
asmlinkage void sha256_block_data_order(u32 *digest, const void *data,
28-
unsigned int num_blks);
27+
asmlinkage void sha256_block_data_order(struct sha256_state *state,
28+
const u8 *data, int num_blks);
2929

3030
int crypto_sha256_arm_update(struct shash_desc *desc, const u8 *data,
3131
unsigned int len)
3232
{
3333
/* make sure casting to sha256_block_fn() is safe */
3434
BUILD_BUG_ON(offsetof(struct sha256_state, state) != 0);
3535

36-
return sha256_base_do_update(desc, data, len,
37-
(sha256_block_fn *)sha256_block_data_order);
36+
return sha256_base_do_update(desc, data, len, sha256_block_data_order);
3837
}
3938
EXPORT_SYMBOL(crypto_sha256_arm_update);
4039

4140
static int crypto_sha256_arm_final(struct shash_desc *desc, u8 *out)
4241
{
43-
sha256_base_do_finalize(desc,
44-
(sha256_block_fn *)sha256_block_data_order);
42+
sha256_base_do_finalize(desc, sha256_block_data_order);
4543
return sha256_base_finish(desc, out);
4644
}
4745

4846
int crypto_sha256_arm_finup(struct shash_desc *desc, const u8 *data,
4947
unsigned int len, u8 *out)
5048
{
51-
sha256_base_do_update(desc, data, len,
52-
(sha256_block_fn *)sha256_block_data_order);
49+
sha256_base_do_update(desc, data, len, sha256_block_data_order);
5350
return crypto_sha256_arm_final(desc, out);
5451
}
5552
EXPORT_SYMBOL(crypto_sha256_arm_finup);

‎arch/arm/crypto/sha512-glue.c‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -25,27 +25,25 @@ MODULE_ALIAS_CRYPTO("sha512");
2525
MODULE_ALIAS_CRYPTO("sha384-arm");
2626
MODULE_ALIAS_CRYPTO("sha512-arm");
2727

28-
asmlinkage void sha512_block_data_order(u64 *state, u8 const *src, int blocks);
28+
asmlinkage void sha512_block_data_order(struct sha512_state *state,
29+
u8 const *src, int blocks);
2930

3031
int sha512_arm_update(struct shash_desc *desc, const u8 *data,
3132
unsigned int len)
3233
{
33-
return sha512_base_do_update(desc, data, len,
34-
(sha512_block_fn *)sha512_block_data_order);
34+
return sha512_base_do_update(desc, data, len, sha512_block_data_order);
3535
}
3636

3737
static int sha512_arm_final(struct shash_desc *desc, u8 *out)
3838
{
39-
sha512_base_do_finalize(desc,
40-
(sha512_block_fn *)sha512_block_data_order);
39+
sha512_base_do_finalize(desc, sha512_block_data_order);
4140
return sha512_base_finish(desc, out);
4241
}
4342

4443
int sha512_arm_finup(struct shash_desc *desc, const u8 *data,
4544
unsigned int len, u8 *out)
4645
{
47-
sha512_base_do_update(desc, data, len,
48-
(sha512_block_fn *)sha512_block_data_order);
46+
sha512_base_do_update(desc, data, len, sha512_block_data_order);
4947
return sha512_arm_final(desc, out);
5048
}
5149

‎arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -180,9 +180,6 @@
180180
brcm,num-gphy = <5>;
181181
brcm,num-rgmii-ports = <2>;
182182

183-
#address-cells = <1>;
184-
#size-cells = <0>;
185-
186183
ports: ports {
187184
#address-cells = <1>;
188185
#size-cells = <0>;

‎arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts‎

Lines changed: 42 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -191,8 +191,10 @@
191191
};
192192

193193
&usdhc2 {
194-
pinctrl-names = "default";
194+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
195195
pinctrl-0 = <&pinctrl_usdhc2>;
196+
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
197+
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
196198
vmmc-supply = <&reg_vdd_3v3>;
197199
vqmmc-supply = <&reg_nvcc_sd>;
198200
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
@@ -275,8 +277,8 @@
275277

276278
pinctrl_i2c4: i2c4grp {
277279
fsl,pins = <
278-
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
279-
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
280+
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083
281+
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083
280282
>;
281283
};
282284

@@ -288,19 +290,19 @@
288290

289291
pinctrl_uart1: uart1grp {
290292
fsl,pins = <
291-
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
292-
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
293-
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
294-
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
293+
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0
294+
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0
295+
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0
296+
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0
295297
>;
296298
};
297299

298300
pinctrl_uart2: uart2grp {
299301
fsl,pins = <
300-
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
301-
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
302-
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
303-
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
302+
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0
303+
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0
304+
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0
305+
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0
304306
>;
305307
};
306308

@@ -312,13 +314,40 @@
312314

313315
pinctrl_usdhc2: usdhc2grp {
314316
fsl,pins = <
315-
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
317+
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90
316318
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
317319
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
318320
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
319321
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
320322
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
321-
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
323+
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
324+
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
325+
>;
326+
};
327+
328+
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
329+
fsl,pins = <
330+
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94
331+
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
332+
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
333+
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
334+
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
335+
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
336+
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
337+
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
338+
>;
339+
};
340+
341+
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
342+
fsl,pins = <
343+
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96
344+
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
345+
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
346+
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
347+
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
348+
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
349+
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
350+
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
322351
>;
323352
};
324353
};

‎arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -220,8 +220,8 @@
220220

221221
pinctrl_i2c1: i2c1grp {
222222
fsl,pins = <
223-
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
224-
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
223+
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
224+
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
225225
>;
226226
};
227227

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