@@ -660,7 +660,7 @@ module RangeStage<
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* - `upper = false` : `v >= b + delta`
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*/
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private predicate boundedSsa (
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- SemSsaVariable v , SemSsaReadPosition pos , SemBound b , D:: Delta delta , boolean upper ,
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+ SemSsaVariable v , SemBound b , D:: Delta delta , SemSsaReadPosition pos , boolean upper ,
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boolean fromBackEdge , D:: Delta origdelta , SemReason reason
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) {
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exists ( SemExpr mid , D:: Delta d1 , D:: Delta d2 , SemReason r1 , SemReason r2 |
@@ -673,10 +673,13 @@ module RangeStage<
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)
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or
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exists ( D:: Delta d , SemReason r1 , SemReason r2 |
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- boundedSsa ( v , pos , b , d , upper , fromBackEdge , origdelta , r2 ) or
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- boundedPhi ( v , b , d , upper , fromBackEdge , origdelta , r2 )
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+ boundedSsa ( pragma [ only_bind_into ] ( v ) , pragma [ only_bind_into ] ( b ) , pragma [ only_bind_into ] ( d ) ,
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+ pragma [ only_bind_into ] ( pos ) , upper , fromBackEdge , origdelta , r2 )
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+ or
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+ boundedPhi ( pragma [ only_bind_into ] ( v ) , pragma [ only_bind_into ] ( b ) , pragma [ only_bind_into ] ( d ) ,
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+ upper , fromBackEdge , origdelta , r2 )
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|
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- unequalIntegralSsa ( v , pos , b , d , r1 ) and
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+ unequalIntegralSsa ( v , b , d , pos , r1 ) and
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(
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upper = true and delta = D:: fromFloat ( D:: toFloat ( d ) - 1 )
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or
@@ -694,7 +697,7 @@ module RangeStage<
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* Holds if `v != b + delta` at `pos` and `v` is of integral type.
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*/
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private predicate unequalIntegralSsa (
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- SemSsaVariable v , SemSsaReadPosition pos , SemBound b , D:: Delta delta , SemReason reason
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+ SemSsaVariable v , SemBound b , D:: Delta delta , SemSsaReadPosition pos , SemReason reason
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) {
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exists ( SemExpr e , D:: Delta d1 , D:: Delta d2 |
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unequalFlowStepIntegralSsa ( v , pos , e , d1 , reason ) and
@@ -746,7 +749,7 @@ module RangeStage<
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) {
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edge .phiInput ( phi , inp ) and
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exists ( D:: Delta d , boolean fromBackEdge0 |
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- boundedSsa ( inp , edge , b , d , upper , fromBackEdge0 , origdelta , reason )
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+ boundedSsa ( inp , b , d , edge , upper , fromBackEdge0 , origdelta , reason )
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or
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boundedPhi ( inp , b , d , upper , fromBackEdge0 , origdelta , reason )
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or
@@ -1022,7 +1025,7 @@ module RangeStage<
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reason = TSemNoReason ( )
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or
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exists ( SemSsaVariable v , SemSsaReadPositionBlock bb |
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- boundedSsa ( v , bb , b , delta , upper , fromBackEdge , origdelta , reason ) and
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+ boundedSsa ( v , b , delta , bb , upper , fromBackEdge , origdelta , reason ) and
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e = v .getAUse ( ) and
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bb .getBlock ( ) = e .getBasicBlock ( )
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)
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