Skip to content

Commit 223b74c

Browse files
arsenmmiguelcsx
authored andcommitted
ARM: Move ABI enum from TargetMachine to TargetParser (llvm#144725)
Consolidate ABI parsing logic in TargetParser where computeDefaultTargetABI is defined, instead of splitting it into the backend. We need the full ABI information computable in RuntimeLibcallsInfo
1 parent f2cd654 commit 223b74c

File tree

5 files changed

+53
-55
lines changed

5 files changed

+53
-55
lines changed

llvm/include/llvm/TargetParser/ARMTargetParser.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,13 @@ class Triple;
2727

2828
namespace ARM {
2929

30+
enum ARMABI {
31+
ARM_ABI_UNKNOWN,
32+
ARM_ABI_APCS,
33+
ARM_ABI_AAPCS, // ARM EABI
34+
ARM_ABI_AAPCS16
35+
};
36+
3037
// Arch extension modifiers for CPUs.
3138
// Note that this is not the same as the AArch64 list
3239
enum ArchExtKind : uint64_t {
@@ -265,6 +272,9 @@ LLVM_ABI unsigned parseArchVersion(StringRef Arch);
265272
LLVM_ABI void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
266273
LLVM_ABI StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
267274

275+
LLVM_ABI ARMABI computeTargetABI(const Triple &TT, StringRef CPU,
276+
StringRef ABIName = "");
277+
268278
/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
269279
///
270280
/// \param Arch the architecture name (e.g., "armv7s"). If it is an empty

llvm/lib/Target/ARM/ARMTargetMachine.cpp

Lines changed: 8 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -121,29 +121,10 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
121121
return std::make_unique<ARMElfTargetObjectFile>();
122122
}
123123

124-
static ARMBaseTargetMachine::ARMABI
125-
computeTargetABI(const Triple &TT, StringRef CPU,
126-
const TargetOptions &Options) {
127-
StringRef ABIName = Options.MCOptions.getABIName();
128-
129-
if (ABIName.empty())
130-
ABIName = ARM::computeDefaultTargetABI(TT, CPU);
131-
132-
if (ABIName == "aapcs16")
133-
return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
134-
else if (ABIName.starts_with("aapcs"))
135-
return ARMBaseTargetMachine::ARM_ABI_AAPCS;
136-
else if (ABIName.starts_with("apcs"))
137-
return ARMBaseTargetMachine::ARM_ABI_APCS;
138-
139-
llvm_unreachable("Unhandled/unknown ABI Name!");
140-
return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
141-
}
142-
143124
static std::string computeDataLayout(const Triple &TT, StringRef CPU,
144125
const TargetOptions &Options,
145126
bool isLittle) {
146-
auto ABI = computeTargetABI(TT, CPU, Options);
127+
auto ABI = ARM::computeTargetABI(TT, CPU, Options.MCOptions.ABIName);
147128
std::string Ret;
148129

149130
if (isLittle)
@@ -163,19 +144,19 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
163144
Ret += "-Fi8";
164145

165146
// ABIs other than APCS have 64 bit integers with natural alignment.
166-
if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
147+
if (ABI != ARM::ARM_ABI_APCS)
167148
Ret += "-i64:64";
168149

169150
// We have 64 bits floats. The APCS ABI requires them to be aligned to 32
170151
// bits, others to 64 bits. We always try to align to 64 bits.
171-
if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
152+
if (ABI == ARM::ARM_ABI_APCS)
172153
Ret += "-f64:32:64";
173154

174155
// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
175156
// to 64. We always ty to give them natural alignment.
176-
if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
157+
if (ABI == ARM::ARM_ABI_APCS)
177158
Ret += "-v64:32:64-v128:32:128";
178-
else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
159+
else if (ABI != ARM::ARM_ABI_AAPCS16)
179160
Ret += "-v128:64:128";
180161

181162
// Try to align aggregates to 32 bits (the default is 64 bits, which has no
@@ -187,9 +168,9 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
187168

188169
// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
189170
// aligned everywhere else.
190-
if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
171+
if (TT.isOSNaCl() || ABI == ARM::ARM_ABI_AAPCS16)
191172
Ret += "-S128";
192-
else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
173+
else if (ABI == ARM::ARM_ABI_AAPCS)
193174
Ret += "-S64";
194175
else
195176
Ret += "-S32";
@@ -226,7 +207,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
226207
TT, CPU, FS, Options,
227208
getEffectiveRelocModel(TT, RM),
228209
getEffectiveCodeModel(CM, CodeModel::Small), OL),
229-
TargetABI(computeTargetABI(TT, CPU, Options)),
210+
TargetABI(ARM::computeTargetABI(TT, CPU, Options.MCOptions.ABIName)),
230211
TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
231212

232213
// Default to triple-appropriate float ABI
@@ -271,22 +252,6 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
271252

272253
ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
273254

274-
bool ARMBaseTargetMachine::isAPCS_ABI() const {
275-
assert(TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
276-
return TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
277-
}
278-
279-
bool ARMBaseTargetMachine::isAAPCS_ABI() const {
280-
assert(TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
281-
return TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
282-
TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
283-
}
284-
285-
bool ARMBaseTargetMachine::isAAPCS16_ABI() const {
286-
assert(TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
287-
return TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
288-
}
289-
290255
MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
291256
BumpPtrAllocator &Allocator, const Function &F,
292257
const TargetSubtargetInfo *STI) const {

llvm/lib/Target/ARM/ARMTargetMachine.h

Lines changed: 17 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -20,19 +20,15 @@
2020
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
2121
#include "llvm/Support/CodeGen.h"
2222
#include "llvm/Target/TargetMachine.h"
23+
#include "llvm/TargetParser/ARMTargetParser.h"
2324
#include <memory>
2425
#include <optional>
2526

2627
namespace llvm {
2728

2829
class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
2930
public:
30-
enum ARMABI {
31-
ARM_ABI_UNKNOWN,
32-
ARM_ABI_APCS,
33-
ARM_ABI_AAPCS, // ARM EABI
34-
ARM_ABI_AAPCS16
35-
} TargetABI;
31+
ARM::ARMABI TargetABI;
3632

3733
protected:
3834
std::unique_ptr<TargetLoweringObjectFile> TLOF;
@@ -66,9 +62,20 @@ class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
6662
return TLOF.get();
6763
}
6864

69-
bool isAPCS_ABI() const;
70-
bool isAAPCS_ABI() const;
71-
bool isAAPCS16_ABI() const;
65+
bool isAPCS_ABI() const {
66+
assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
67+
return TargetABI == ARM::ARM_ABI_APCS;
68+
}
69+
70+
bool isAAPCS_ABI() const {
71+
assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
72+
return TargetABI == ARM::ARM_ABI_AAPCS || TargetABI == ARM::ARM_ABI_AAPCS16;
73+
}
74+
75+
bool isAAPCS16_ABI() const {
76+
assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
77+
return TargetABI == ARM::ARM_ABI_AAPCS16;
78+
}
7279

7380
bool isTargetHardFloat() const {
7481
return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
@@ -77,8 +84,7 @@ class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
7784
TargetTriple.getEnvironment() == Triple::EABIHF ||
7885
(TargetTriple.isOSBinFormatMachO() &&
7986
TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) ||
80-
TargetTriple.isOSWindows() ||
81-
TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
87+
TargetTriple.isOSWindows() || TargetABI == ARM::ARM_ABI_AAPCS16;
8288
}
8389

8490
bool targetSchedulesPostRAScheduling() const override { return true; };

llvm/lib/Target/ARM/ARMTargetObjectFile.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ ARMElfTargetObjectFile::ARMElfTargetObjectFile() {
3737
void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
3838
const TargetMachine &TM) {
3939
const ARMBaseTargetMachine &ARM_TM = static_cast<const ARMBaseTargetMachine &>(TM);
40-
bool isAAPCS_ABI = ARM_TM.TargetABI == ARMBaseTargetMachine::ARMABI::ARM_ABI_AAPCS;
40+
bool isAAPCS_ABI = ARM_TM.TargetABI == ARM::ARMABI::ARM_ABI_AAPCS;
4141
bool genExecuteOnly =
4242
ARM_TM.getMCSubtargetInfo()->hasFeature(ARM::FeatureExecuteOnly);
4343

llvm/lib/TargetParser/ARMTargetParser.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -575,6 +575,23 @@ StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
575575
}
576576
}
577577

578+
ARM::ARMABI ARM::computeTargetABI(const Triple &TT, StringRef CPU,
579+
StringRef ABIName) {
580+
if (ABIName.empty())
581+
ABIName = ARM::computeDefaultTargetABI(TT, CPU);
582+
583+
if (ABIName == "aapcs16")
584+
return ARM_ABI_AAPCS16;
585+
586+
if (ABIName.starts_with("aapcs"))
587+
return ARM_ABI_AAPCS;
588+
589+
if (ABIName.starts_with("apcs"))
590+
return ARM_ABI_APCS;
591+
592+
return ARM_ABI_UNKNOWN;
593+
}
594+
578595
StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
579596
if (MArch.empty())
580597
MArch = Triple.getArchName();

0 commit comments

Comments
 (0)