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CodeGen: Emit error if getRegisterByName fails (llvm#145194)
This avoids using report_fatal_error and standardizes the error message in a subset of the error conditions.
1 parent 5768f2e commit 2a6808b

29 files changed

+222
-117
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9107,8 +9107,18 @@ LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) {
91079107
cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0));
91089108

91099109
Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF);
9110-
if (!PhysReg.isValid())
9111-
return UnableToLegalize;
9110+
if (!PhysReg) {
9111+
const Function &Fn = MF.getFunction();
9112+
Fn.getContext().diagnose(DiagnosticInfoGenericWithLoc(
9113+
"invalid register \"" + Twine(RegStr->getString().data()) + "\" for " +
9114+
(IsRead ? "llvm.read_register" : "llvm.write_register"),
9115+
Fn, MI.getDebugLoc()));
9116+
if (IsRead)
9117+
MIRBuilder.buildUndef(ValReg);
9118+
9119+
MI.eraseFromParent();
9120+
return Legalized;
9121+
}
91129122

91139123
if (IsRead)
91149124
MIRBuilder.buildCopy(ValReg, PhysReg);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Lines changed: 36 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2460,11 +2460,25 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
24602460

24612461
EVT VT = Op->getValueType(0);
24622462
LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
2463-
Register Reg =
2464-
TLI->getRegisterByName(RegStr->getString().data(), Ty,
2465-
CurDAG->getMachineFunction());
2466-
SDValue New = CurDAG->getCopyFromReg(
2467-
Op->getOperand(0), dl, Reg, Op->getValueType(0));
2463+
2464+
const MachineFunction &MF = CurDAG->getMachineFunction();
2465+
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
2466+
2467+
SDValue New;
2468+
if (!Reg) {
2469+
const Function &Fn = MF.getFunction();
2470+
Fn.getContext().diagnose(DiagnosticInfoGenericWithLoc(
2471+
"invalid register \"" + Twine(RegStr->getString().data()) +
2472+
"\" for llvm.read_register",
2473+
Fn, Op->getDebugLoc()));
2474+
New =
2475+
SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0);
2476+
ReplaceUses(SDValue(Op, 1), Op->getOperand(0));
2477+
} else {
2478+
New =
2479+
CurDAG->getCopyFromReg(Op->getOperand(0), dl, Reg, Op->getValueType(0));
2480+
}
2481+
24682482
New->setNodeId(-1);
24692483
ReplaceUses(Op, New.getNode());
24702484
CurDAG->RemoveDeadNode(Op);
@@ -2478,12 +2492,23 @@ void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
24782492
EVT VT = Op->getOperand(2).getValueType();
24792493
LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
24802494

2481-
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty,
2482-
CurDAG->getMachineFunction());
2483-
SDValue New = CurDAG->getCopyToReg(
2484-
Op->getOperand(0), dl, Reg, Op->getOperand(2));
2485-
New->setNodeId(-1);
2486-
ReplaceUses(Op, New.getNode());
2495+
const MachineFunction &MF = CurDAG->getMachineFunction();
2496+
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
2497+
2498+
if (!Reg) {
2499+
const Function &Fn = MF.getFunction();
2500+
Fn.getContext().diagnose(DiagnosticInfoGenericWithLoc(
2501+
"invalid register \"" + Twine(RegStr->getString().data()) +
2502+
"\" for llvm.write_register",
2503+
Fn, Op->getDebugLoc()));
2504+
ReplaceUses(SDValue(Op, 0), Op->getOperand(0));
2505+
} else {
2506+
SDValue New =
2507+
CurDAG->getCopyToReg(Op->getOperand(0), dl, Reg, Op->getOperand(2));
2508+
New->setNodeId(-1);
2509+
ReplaceUses(Op, New.getNode());
2510+
}
2511+
24872512
CurDAG->RemoveDeadNode(Op);
24882513
}
24892514

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11977,12 +11977,9 @@ getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const
1197711977
unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false);
1197811978
if (!Subtarget->isXRegisterReserved(DwarfRegNum) &&
1197911979
!MRI->isReservedReg(MF, Reg))
11980-
Reg = 0;
11980+
Reg = Register();
1198111981
}
11982-
if (Reg)
11983-
return Reg;
11984-
report_fatal_error(Twine("Invalid register name \""
11985-
+ StringRef(RegName) + "\"."));
11982+
return Reg;
1198611983
}
1198711984

1198811985
SDValue AArch64TargetLowering::LowerADDROFRETURNADDR(SDValue Op,

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4492,11 +4492,8 @@ Register SITargetLowering::getRegisterByName(const char *RegName, LLT VT,
44924492
.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
44934493
.Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
44944494
.Default(Register());
4495-
4496-
if (Reg == AMDGPU::NoRegister) {
4497-
report_fatal_error(
4498-
Twine("invalid register name \"" + StringRef(RegName) + "\"."));
4499-
}
4495+
if (!Reg)
4496+
return Reg;
45004497

45014498
if (!Subtarget->hasFlatScrRegister() &&
45024499
Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6166,13 +6166,9 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
61666166
// this table could be generated automatically from RegInfo.
61676167
Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
61686168
const MachineFunction &MF) const {
6169-
Register Reg = StringSwitch<unsigned>(RegName)
6170-
.Case("sp", ARM::SP)
6171-
.Default(0);
6172-
if (Reg)
6173-
return Reg;
6174-
report_fatal_error(Twine("Invalid register name \""
6175-
+ StringRef(RegName) + "\"."));
6169+
return StringSwitch<Register>(RegName)
6170+
.Case("sp", ARM::SP)
6171+
.Default(Register());
61766172
}
61776173

61786174
// Result is 64 bit value so split into two 32 bit values and return as a

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -329,10 +329,7 @@ Register HexagonTargetLowering::getRegisterByName(
329329
.Case("cs0", Hexagon::CS0)
330330
.Case("cs1", Hexagon::CS1)
331331
.Default(Register());
332-
if (Reg)
333-
return Reg;
334-
335-
report_fatal_error("Invalid register name global variable");
332+
return Reg;
336333
}
337334

338335
/// LowerCallResult - Lower the result values of an ISD::CALL into the

‎llvm/lib/Target/Lanai/LanaiISelLowering.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,7 @@ Register LanaiTargetLowering::getRegisterByName(
211211
const char *RegName, LLT /*VT*/,
212212
const MachineFunction & /*MF*/) const {
213213
// Only unallocatable registers should be matched here.
214-
Register Reg = StringSwitch<unsigned>(RegName)
214+
Register Reg = StringSwitch<Register>(RegName)
215215
.Case("pc", Lanai::PC)
216216
.Case("sp", Lanai::SP)
217217
.Case("fp", Lanai::FP)
@@ -220,11 +220,8 @@ Register LanaiTargetLowering::getRegisterByName(
220220
.Case("rr2", Lanai::RR2)
221221
.Case("r11", Lanai::R11)
222222
.Case("rca", Lanai::RCA)
223-
.Default(0);
224-
225-
if (Reg)
226-
return Reg;
227-
report_fatal_error("Invalid register name global variable");
223+
.Default(Register());
224+
return Reg;
228225
}
229226

230227
std::pair<unsigned, const TargetRegisterClass *>

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7957,11 +7957,10 @@ LoongArchTargetLowering::getRegisterByName(const char *RegName, LLT VT,
79577957
std::pair<StringRef, StringRef> Name = StringRef(RegName).split('$');
79587958
std::string NewRegName = Name.second.str();
79597959
Register Reg = MatchRegisterAltName(NewRegName);
7960-
if (Reg == LoongArch::NoRegister)
7960+
if (!Reg)
79617961
Reg = MatchRegisterName(NewRegName);
7962-
if (Reg == LoongArch::NoRegister)
7963-
report_fatal_error(
7964-
Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
7962+
if (!Reg)
7963+
return Reg;
79657964
BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF);
79667965
if (!ReservedRegs.test(Reg))
79677966
report_fatal_error(Twine("Trying to obtain non-reserved register \"" +

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4969,17 +4969,14 @@ MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
49694969
.Case("$28", Mips::GP_64)
49704970
.Case("sp", Mips::SP_64)
49714971
.Default(Register());
4972-
if (Reg)
4973-
return Reg;
4974-
} else {
4975-
Register Reg = StringSwitch<Register>(RegName)
4976-
.Case("$28", Mips::GP)
4977-
.Case("sp", Mips::SP)
4978-
.Default(Register());
4979-
if (Reg)
4980-
return Reg;
4972+
return Reg;
49814973
}
4982-
report_fatal_error("Invalid register name global variable");
4974+
4975+
Register Reg = StringSwitch<Register>(RegName)
4976+
.Case("$28", Mips::GP)
4977+
.Case("sp", Mips::SP)
4978+
.Default(Register());
4979+
return Reg;
49834980
}
49844981

49854982
MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17984,8 +17984,7 @@ Register PPCTargetLowering::getRegisterByName(const char *RegName, LLT VT,
1798417984

1798517985
Register Reg = MatchRegisterName(RegName);
1798617986
if (!Reg)
17987-
report_fatal_error(
17988-
Twine("Invalid global name register \"" + StringRef(RegName) + "\"."));
17987+
return Reg;
1798917988

1799017989
// FIXME: Unable to generate code for `-O2` but okay for `-O0`.
1799117990
// Need followup investigation as to why.

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