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1 parent acdc1d7 commit f1d2eb8Copy full SHA for f1d2eb8
src/plan/generational/immix/global.rs
@@ -130,7 +130,6 @@ impl<VM: VMBinding> Plan for GenImmix<VM> {
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self.gen.prepare(tls);
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if full_heap {
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if VM::VMObjectModel::GLOBAL_LOG_BIT_SPEC.is_on_side() {
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- self.gen.common.clear_side_log_bits();
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self.immix_space.clear_side_log_bits();
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}
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self.immix_space.prepare(
src/plan/sticky/immix/global.rs
@@ -124,7 +124,6 @@ impl<VM: VMBinding> Plan for StickyImmix<VM> {
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} else {
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self.full_heap_gc_count.lock().unwrap().inc();
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- self.immix.common.clear_side_log_bits();
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self.immix.immix_space.clear_side_log_bits();
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self.immix.prepare(tls);
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