Clear side log bits for full heap genimmix

qinsoon · qinsoon · commit fc8e662a79fb · 2025-08-14T00:30:54.000Z
diff --git a/src/plan/generational/immix/global.rs b/src/plan/generational/immix/global.rs
@@ -130,6 +130,7 @@ impl<VM: VMBinding> Plan for GenImmix<VM> {
         self.gen.prepare(tls);
         if full_heap {
             if VM::VMObjectModel::GLOBAL_LOG_BIT_SPEC.is_on_side() {
+                self.gen.common.clear_side_log_bits();
                 self.immix_space.clear_side_log_bits();
             }
             self.immix_space.prepare(

Original file line number	Diff line number	Diff line change
`@@ -130,6 +130,7 @@ impl<VM: VMBinding> Plan for GenImmix<VM> {`
`130`	`130`	`self.gen.prepare(tls);`
`131`	`131`	`if full_heap {`
`132`	`132`	`if VM::VMObjectModel::GLOBAL_LOG_BIT_SPEC.is_on_side() {`
	`133`	`+ self.gen.common.clear_side_log_bits();`
`133`	`134`	`self.immix_space.clear_side_log_bits();`
`134`	`135`	`}`
`135`	`136`	`self.immix_space.prepare(`