More assertions

Author: caizixian

openjdk/cpu/riscv/mmtkObjectBarrierSetAssembler_riscv.cpp

@@ -32,32 +32,34 @@
 //         tail    _Z32object_reference_write_slow_callPvS_m
 void MMTkObjectBarrierSetAssembler::object_reference_write_post(MacroAssembler* masm, DecoratorSet decorators, Address dst, Register val, Register tmp1, Register tmp2) const {
   // tmp1 and tmp2 is from MacroAssembler::access_store_at
-  // See tmplateTable_riscv, we don't actually get any temporary register.
+  // For do_oop_store, we have three tmps, x28/t3, x29/t4, x13/a3
   // printf("object_reference_write_post\n");
   if (can_remove_barrier(decorators, val, /* skip_const_null */ true)) return;
-#if MMTK_ENABLE_BARRIER_FASTPATH
-  Label done;
-
   Register obj = dst.base();
   assert(obj->is_valid(), "dst must be an offset from a base register");
-  assert_different_registers(obj, t0, t1);
-  assert_different_registers(val, t0, t1);
-
-  // t0 = load-byte (SIDE_METADATA_BASE_ADDRESS + (obj >> 6));
-  __ mv(t0, obj);
-  __ srli(t0, t0, 6); // t0 = obj >> 6;
-  __ li(t1, SIDE_METADATA_BASE_ADDRESS);
-  __ add(t0, t0, t1); // t0 = SIDE_METADATA_BASE_ADDRESS + (obj >> 6);
-  __ lbu(t0, Address(t0, 0));
-  // t1 = (obj >> 3) & 7
-  __ mv(t1, obj);
-  __ srli(t1, t1, 3);
-  __ andi(t1, t1, 7);
-  // t0 = t0 >> t1
-  __ sraw(t0, t0, t1);
-  // if ((t0 & 1) == 1) fall through to slowpath;
-  __ andi(t0, t0, 1);
-  __ bnez(t0, done); // (t0 & 1) == 1 is equivalent to (t0 & 1) != 0
+  RegSet saved = RegSet::of(obj); // see void G1BarrierSetAssembler::g1_write_barrier_post
+  __ push_reg(saved, sp);
+#if MMTK_ENABLE_BARRIER_FASTPATH
+  Label done;
+  assert_different_registers(obj, tmp1, tmp2);
+  assert_different_registers(val, tmp1, tmp2);
+  assert(tmp1->is_valid(), "need temp reg");
+  assert(tmp2->is_valid(), "need temp reg");
+  // tmp1 = load-byte (SIDE_METADATA_BASE_ADDRESS + (obj >> 6));
+  __ mv(tmp1, obj);
+  __ srli(tmp1, tmp1, 6); // tmp1 = obj >> 6;
+  __ li(tmp2, SIDE_METADATA_BASE_ADDRESS);
+  __ add(tmp1, tmp1, tmp2); // tmp1 = SIDE_METADATA_BASE_ADDRESS + (obj >> 6);
+  __ lbu(tmp1, Address(tmp1, 0));
+  // tmp2 = (obj >> 3) & 7
+  __ mv(tmp2, obj);
+  __ srli(tmp2, tmp2, 3);
+  __ andi(tmp2, tmp2, 7);
+  // tmp1 = tmp1 >> tmp2
+  __ sraw(tmp1, tmp1, tmp2);
+  // if ((tmp1 & 1) == 1) fall through to slowpath;
+  __ andi(tmp1, tmp1, 1);
+  __ bnez(tmp1, done); // (tmp1 & 1) == 1 is equivalent to (tmp1 & 1) != 0
   // setup calling convention
   __ mv(c_rarg0, obj);
   __ la(c_rarg1, dst);
@@ -71,6 +73,7 @@ void MMTkObjectBarrierSetAssembler::object_reference_write_post(MacroAssembler*
   __ mv(c_rarg2, val == noreg ? zr : val);
   __ call_VM_leaf_base(FN_ADDR(MMTkBarrierSetRuntime::object_reference_write_post_call), 3);
 #endif
+  __ pop_reg(saved, sp);
 }
 
 void MMTkObjectBarrierSetAssembler::arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,

openjdk/cpu/x86/mmtkObjectBarrierSetAssembler_x86.cpp

@@ -45,9 +45,14 @@ void MMTkObjectBarrierSetAssembler::object_reference_write_post(MacroAssembler*
 
   __ bind(done);
 #else
+  Register obj = dst.base();
   __ movptr(c_rarg0, obj);
   __ lea(c_rarg1, dst);
-  __ movptr(c_rarg2, val == noreg ?  (int32_t) NULL_WORD : val);
+  if (val == noreg) {
+    __ movptr(c_rarg2, NULL_WORD);
+  } else {
+    __ movptr(c_rarg2, val);
+  }
   __ call_VM_leaf_base(FN_ADDR(MMTkBarrierSetRuntime::object_reference_write_post_call), 3);
 #endif
 }