Fix typo

Author: bwmf2

stdarch/crates/core_arch/src/aarch64/neon/generated.rs

@@ -16978,7 +16978,7 @@ pub unsafe fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x
     simd_add(a, simd_cast(f))
 }
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 ///
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)
 #[inline]
@@ -16994,7 +16994,7 @@ pub unsafe fn vqabs_s64(a: int64x1_t) -> int64x1_t {
     vqabs_s64_(a)
 }
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 ///
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)
 #[inline]

stdarch/crates/core_arch/src/arm_shared/neon/generated.rs

@@ -29382,7 +29382,7 @@ pub unsafe fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
     simd_add(a, simd_cast(e))
 }
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 ///
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)
 #[inline]
@@ -29401,7 +29401,7 @@ pub unsafe fn vqabs_s8(a: int8x8_t) -> int8x8_t {
 vqabs_s8_(a)
 }
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 ///
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)
 #[inline]
@@ -29420,7 +29420,7 @@ pub unsafe fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
 vqabsq_s8_(a)
 }
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 ///
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)
 #[inline]
@@ -29439,7 +29439,7 @@ pub unsafe fn vqabs_s16(a: int16x4_t) -> int16x4_t {
 vqabs_s16_(a)
 }
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 ///
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)
 #[inline]
@@ -29458,7 +29458,7 @@ pub unsafe fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
 vqabsq_s16_(a)
 }
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 ///
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)
 #[inline]
@@ -29477,7 +29477,7 @@ pub unsafe fn vqabs_s32(a: int32x2_t) -> int32x2_t {
 vqabs_s32_(a)
 }
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 ///
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)
 #[inline]

stdarch/crates/core_arch/src/riscv_shared/mod.rs

@@ -488,7 +488,7 @@ pub unsafe fn hinval_gvma_all() {
 /// Register `fcsr` is a 32-bit read/write register that selects the dynamic rounding mode
 /// for floating-point arithmetic operations and holds the accrued exception flag.
 ///
-/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
+/// According to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
 /// register `fcsr` is defined as:
 ///
 /// | Bit index | Meaning |
@@ -521,7 +521,7 @@ pub fn fscsr(value: u32) -> u32 {
 
 /// Reads the floating-point rounding mode register `frm`
 ///
-/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
+/// According to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
 /// the rounding mode field is defined as listed in the table below:
 ///
 /// | Rounding Mode | Mnemonic | Meaning |
@@ -558,8 +558,8 @@ pub fn fsrm(value: u32) -> u32 {
 /// The accrued exception flags indicate the exception conditions that have arisen
 /// on any floating-point arithmetic instruction since the field was last reset by software.
 ///
-/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
-/// the accured exception flags is defined as a bit vector of 5 bits.
+/// According to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
+/// the accrued exception flags is defined as a bit vector of 5 bits.
 /// The meaning of each binary bit is listed in the table below.
 ///
 /// | Bit index | Mnemonic | Meaning |

stdarch/crates/core_arch/src/x86/avx2.rs

@@ -2277,7 +2277,7 @@ pub unsafe fn _mm256_permute4x64_pd<const IMM8: i32>(a: __m256d) -> __m256d {
     )
 }
 
-/// Shuffles eight 32-bit foating-point elements in `a` across lanes using
+/// Shuffles eight 32-bit floating-point elements in `a` across lanes using
 /// the corresponding 32-bit integer index in `idx`.
 ///
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutevar8x32_ps)

stdarch/crates/core_arch/src/x86/sse.rs

@@ -1380,7 +1380,7 @@ pub unsafe fn _mm_getcsr() -> u32 {
 
 /// Sets the MXCSR register with the 32-bit unsigned integer value.
 ///
-/// This register constrols how SIMD instructions handle floating point
+/// This register controls how SIMD instructions handle floating point
 /// operations. Modifying this register only affects the current thread.
 ///
 /// It contains several groups of flags:

stdarch/crates/core_arch/src/x86/sse41.rs

@@ -689,7 +689,7 @@ pub unsafe fn _mm_ceil_ps(a: __m128) -> __m128 {
 
 /// Round the lower double-precision (64-bit) floating-point element in `b`
 /// up to an integer value, store the result as a double-precision
-/// floating-point element in the lower element of the intrisic result,
+/// floating-point element in the lower element of the intrinsic result,
 /// and copies the upper element from `a` to the upper element
 /// of the intrinsic result.
 ///

stdarch/crates/std_detect/src/detect/os/linux/aarch64.rs

@@ -227,7 +227,7 @@ impl From<super::cpuinfo::CpuInfo> for AtHwcap {
 impl AtHwcap {
     /// Initializes the cache from the feature -bits.
     ///
-    /// The feature dependencies here come directly from LLVM's feature definintions:
+    /// The feature dependencies here come directly from LLVM's feature definitions:
     /// https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64.td
     fn cache(self, is_exynos9810: bool) -> cache::Initializer {
         let mut value = cache::Initializer::default();

stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs

@@ -52,7 +52,7 @@ pub(crate) struct AuxVec {
 /// Note that run-time feature detection is not invoked for features that can
 /// be detected at compile-time. Also note that if this function returns an
 /// error, cpuinfo still can (and will) be used to try to perform run-time
-/// feature detecton on some platforms.
+/// feature detection on some platforms.
 ///
 /// Note: The `std_detect_dlsym_getauxval` cargo feature is ignored on `*-linux-gnu*` targets,
 /// since [all `*-linux-gnu*` targets ([since Rust 1.64](https://blog.rust-lang.org/2022/08/01/Increasing-glibc-kernel-requirements.html))

stdarch/crates/stdarch-gen/neon.spec

@@ -14,7 +14,7 @@
 // Sections start with EXACTLY three slashes followed
 // by AT LEAST one space. Sections are used for two things:
 //
-// 1) they serve as the doc comment for the given intrinics.
+// 1) they serve as the doc comment for the given intrinsics.
 // 2) they reset all variables (name, fn, etc.)
 //
 // # Variables
@@ -29,16 +29,16 @@
 //           the function will exclusively be generated for
 //           aarch64.
 //           This is used to generate both aarch64 specific and
-//           shared intrinics by first only specifying th aarch64
+//           shared intrinsics by first only specifying th aarch64
 //           variant then the arm variant.
 //
-// arm     - The arm v7 intrinics used to checked for arm code
+// arm     - The arm v7 intrinsics used to checked for arm code
 //           generation. All neon functions available in arm are
-//           also available in aarch64. If no aarch64 intrinic was
+//           also available in aarch64. If no aarch64 intrinsic was
 //           set they are assumed to be the same.
-//           Intrinics ending with a `.` will have a size suffixes
+//           Intrinsics ending with a `.` will have a size suffixes
 //           added (such as `i8` or `i64`) that is not sign specific
-//           Intrinics ending with a `.s` will have a size suffixes
+//           Intrinsics ending with a `.s` will have a size suffixes
 //           added (such as `s8` or `u64`) that is sign specific
 //
 // a       - First input for tests, it gets scaled to the size of
@@ -7490,10 +7490,10 @@ aarch64 = sabal
 generate int64x2_t:int32x4_t:int32x4_t:int64x2_t
 
 ////////////////////
-// Singned saturating Absolute value
+// Signed saturating Absolute value
 ////////////////////
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 name = vqabs
 a = MIN, MAX, -6, -5, -4, -3, -2, -1, 0, -127, 127, 1, 2, 3, 4, 5
 validate MAX, MAX, 6, 5, 4, 3, 2, 1, 0, 127, 127, 1, 2, 3, 4, 5
@@ -7504,7 +7504,7 @@ link-arm = vqabs._EXT_
 link-aarch64 = sqabs._EXT_
 generate int*_t
 
-/// Singned saturating Absolute value
+/// Signed saturating Absolute value
 name = vqabs
 a = MIN, -7
 validate MAX, 7

stdarch/crates/stdarch-test/src/lib.rs

@@ -115,7 +115,7 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str) {
                 "cpuid" => 30,
 
                 // Apparently, on Windows, LLVM generates a bunch of
-                // saves/restores of xmm registers around these intstructions,
+                // saves/restores of xmm registers around these instructions,
                 // which exceeds the limit of 20 below. As it seems dictated by
                 // Windows's ABI (I believe?), we probably can't do much
                 // about it.