Add spin_loop hint for RISC-V architecture

luojia65 · luojia65 · commit d9f810530ec4 · 2021-12-05T16:39:21.000+08:00
This commit also updates `stdarch` git submodule.
diff --git a/core/src/hint.rs b/core/src/hint.rs
@@ -137,6 +137,11 @@ pub fn spin_loop() {
             unsafe { crate::arch::arm::__yield() };
         }
     }
+
+    #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+    {
+        crate::arch::riscv::pause();
+    }
 }
 
 /// An identity function that *__hints__* to the compiler to be maximally pessimistic about what
diff --git a/stdarch b/stdarch
@@ -1 +1 @@
-Subproject commit cfba59fccd90b3b52a614120834320f764ab08d1
+Subproject commit 43b4556c44197af4ef82e42a12dfc513a1397f87

Original file line number	Diff line number	Diff line change
`@@ -137,6 +137,11 @@ pub fn spin_loop() {`
`137`	`137`	`unsafe { crate::arch::arm::__yield() };`
`138`	`138`	`}`
`139`	`139`	`}`
	`140`	`+`
	`141`	`+ #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]`
	`142`	`+ {`
	`143`	`+ crate::arch::riscv::pause();`
	`144`	`+ }`
`140`	`145`	`}`
`141`	`146`
`142`	`147`	`/// An identity function that __hints__ to the compiler to be maximally pessimistic about what`
Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-Subproject commit cfba59fccd90b3b52a614120834320f764ab08d1`
	`1`	`+Subproject commit 43b4556c44197af4ef82e42a12dfc513a1397f87`