[I2S] Setup PLL for the I2S peripheral

Functions are added to be able
to set up the I2S PLL at startup.
PLL multipliers are taken over from ST's example:
STM32F4-Discovery_FW_V1.1.0/Project/Audio_playback_and_record/src/system_stm32f4xx.c

Author: ledneczki

src/modm/board/disco_f407vg/board.hpp

@@ -82,12 +82,17 @@ struct SystemClock {
 	{
 		Rcc::enableExternalCrystal();	// 8MHz
 		const Rcc::PllFactors pllFactors{
-			.pllM = 4,		// 8MHz / M=4 -> 2MHz
-			.pllN = 168,	// 2MHz * N=168 -> 336MHz
+			.pllM = 8,		// 8MHz / M=8 -> 1MHz
+			.pllN = 336,	// 1MHz * N=336 -> 336MHz
 			.pllP = 2,		// 336MHz / P=2 -> 168MHz = F_cpu
 			.pllQ = 7		// 336MHz / Q=7 ->  48MHz = F_usb
 		};
 		Rcc::enablePll(Rcc::PllSource::ExternalCrystal, pllFactors);
+		const Rcc::PllI2sFactors pllI2sFactors{
+			.pllN = 258,	// 1 MHz * N=258 -> 258 MHz
+			.pllR = 3		// 258 MHz / R=3 -> 86 MHz
+		};
+		Rcc::enablePllI2s(Rcc::PllSource::ExternalCrystal, pllI2sFactors, 2048);
 		// set flash latency for 168MHz
 		Rcc::setFlashLatency<Frequency>();
 		// switch system clock to PLL output

src/modm/platform/clock/stm32/module.lb

@@ -70,6 +70,7 @@ def build(env):
         (target["family"] == "l4" and target["name"][0] in ["p", "q", "r", "s"])
     properties["pllsai_p_usb"] = (target["family"] == "f7") or \
         ((target["family"] == "f4") and target["name"] in ["46", "69", "79"])
+    properties["plli2s"] = (target["family"] == "f4")
     properties["cfgr1"] = ("CDCFGR1" if target.name in ["a0", "a3", "b0", "b3"] else "D1CFGR") \
                            if target.family == "h7" else "CFGR"
     properties["d1"] = ("CD" if target.name in ["a0", "a3", "b0", "b3"] else "D1") \

src/modm/platform/clock/stm32/rcc.cpp.in

@@ -305,6 +305,29 @@ Rcc::enablePll{{id}}(PllSource source, const PllFactors& pllFactors, uint32_t wa
 
 %% endfor
 
+%% if plli2s
+bool
+modm::platform::Rcc::enablePllI2s(PllSource, const PllI2sFactors& pllFactors, uint32_t waitCycles)
+{
+	// Read reserved and don't care values and clear all other values
+	uint32_t tmp = RCC->PLLI2SCFGR & ~(RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR);
+	// set PLL divider and multiplier
+	tmp |= (((uint32_t) pllFactors.pllN) << RCC_PLLI2SCFGR_PLLI2SN_Pos) & RCC_PLLI2SCFGR_PLLI2SN;
+	tmp |= (((uint32_t) pllFactors.pllR) << RCC_PLLI2SCFGR_PLLI2SR_Pos) & RCC_PLLI2SCFGR_PLLI2SR;
+	RCC->PLLI2SCFGR = tmp;
+
+	// enable I2S PLL
+	RCC->CR |= RCC_CR_PLLI2SON;
+	// wait till I2S PLL gets ready or time is up
+	while ((RCC->CR & RCC_CR_PLLI2SRDY) == 0)
+	{
+		if (not --waitCycles)
+			return false;
+	}
+	return true;
+}
+%% endif
+
 %% if pllsai_p_usb
 bool
 Rcc::enablePllSai(const PllSaiFactors& pllFactors, uint32_t waitCycles)

src/modm/platform/clock/stm32/rcc.hpp.in

@@ -609,6 +609,32 @@ public:
 	setHsiPredivider4Enabled(bool divideBy4, uint32_t waitCycles = 2048);
 %% endif
 
+%% if target["family"] == "f4"
+	/** TODO: comments
+	 * input clock is the HSE or HSI divided by M
+	 * f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)
+	 * f(PLL I2S clock output) = f(VCO clock) / PLLI2SR
+	 * 
+	 * \param	pllN
+	 * PLLI2S multiplication factor for VCO
+	 * 50 <= PLLI2SN <= 432
+	 * 
+	 * \param	pllR
+	 * PLLI2S division factor for I2S clocks
+	 * Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.
+	 * 2 <= PLLR <= 7
+	 */
+	struct PllI2sFactors
+	{
+		const uint16_t pllN;
+		const uint16_t pllR;
+	};
+
+	/* TODO: comments */
+	static bool
+	enablePllI2s(PllSource, const PllI2sFactors& pllFactors, uint32_t waitCycles);
+%% endif
+
 	// sinks
 	static bool
 	enableSystemClock(SystemClockSource src, uint32_t waitCycles = 2048);