@@ -66,7 +66,6 @@ SRAMs explicitly to free up the space in the lower sections.
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│ .fastdata │
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│ .fastcode │
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│ (.vector_ram) │◄ only if remapped into RAM
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- │ +PROCESS_STACK_SIZE │◄ __ process_stack_top
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SRAM1 │ +MAIN_STACK_SIZE │◄ __ main_stack_top
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0x2000 0000 └────────────────────────┘◄ __ sram1_start
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@@ -135,7 +134,6 @@ Therefore the main stack is placed into SRAM, even though it is slower than CCM.
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│ .data │
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│ .fastcode │
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│ (.vector_ram) │◄ only if remapped into RAM
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- │ +PROCESS_STACK_SIZE │◄ __ process_stack_top
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SRAM1 │ +MAIN_STACK_SIZE │◄ __ main_stack_top
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0x2000 0000 └────────────────────────┘◄ __ sram1_start
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@@ -205,7 +203,6 @@ not DMA-able.
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│ .bss │
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│ .data_sram1 │
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│ .data │
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- │ +PROCESS_STACK_SIZE │◄ __ process_stack_top
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SRAM1 │ +MAIN_STACK_SIZE │◄ __ main_stack_top
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0x2000 0000 └────────────────────────┘◄ __ sram1_start
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@@ -285,7 +282,6 @@ overflow into the SRAM1/2 sections.
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access │ .data_dtcm │
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│ .data │
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│ .fastdata │
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- │ +PROCESS_STACK_SIZE │◄ __ process_stack_top
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DTCM │ +MAIN_STACK_SIZE │◄ __ main_stack_top
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0x2000 0000 └────────────────────────┘◄ __ dtcm_start
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@@ -391,7 +387,6 @@ placed into the 128kB DTCM, but cannot overflow into D1_SRAM section.
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only │ .data_dtcm │
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access │ .data │
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│ .fastdata │
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- │ +PROCESS_STACK_SIZE │◄ __ process_stack_top
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DTCM │ +MAIN_STACK_SIZE │◄ __ main_stack_top
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0x2000 0000 └────────────────────────┘◄ __ dtcm_start
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