[platform] DMA: Enable for many more stm32-channel(-request) devices

Author: rleh

README.md

@@ -185,16 +185,16 @@ Please [discover modm's peripheral drivers for your specific device][discover].
 <td align="center">✗</td>
 </tr><tr>
 <td align="left">DMA</td>
+<td align="center">✅</td>
+<td align="center">✅</td>
 <td align="center">○</td>
+<td align="center">✅</td>
 <td align="center">○</td>
 <td align="center">○</td>
 <td align="center">○</td>
 <td align="center">○</td>
-<td align="center">○</td>
-<td align="center">○</td>
-<td align="center">○</td>
-<td align="center">○</td>
-<td align="center">○</td>
+<td align="center">✅</td>
+<td align="center">✅</td>
 <td align="center">✅</td>
 <td align="center">○</td>
 <td align="center">✗</td>

src/modm/platform/dma/stm32/dma.cpp.in

@@ -11,16 +11,19 @@
 
 #include "dma.hpp"
 
-%% for channels in dma["channels"]
+using namespace modm::platform;
+
+%% for instance, irqs in irqList.items()
 /*
- * IRQ handler for DMA{{ channels.instance }}
+ * IRQ handler for DMA{{ instance }}
  */
-%% for channel in channels.channel
+%% for channels in irqs
 
-MODM_ISR(DMA{{ channels.instance }}_Channel{{ channel.position }})
+MODM_ISR(DMA{{ instance }}_Channel{{ channels | join("_") }})
 {
-	using namespace modm::platform;
-	Dma{{ channels.instance }}::Channel<DmaBase::Channel::Channel{{ channel.position }}>::interruptHandler();
+	%% for channel in channels
+	Dma{{ instance }}::Channel<DmaBase::Channel::Channel{{ channel }}>::interruptHandler();
+	%% endfor
 }
 
 %% endfor

src/modm/platform/dma/stm32/dma.hpp.in

@@ -2,6 +2,7 @@
  * Copyright (c) 2014, Kevin Läufer
  * Copyright (c) 2014-2017, Niklas Hauser
  * Copyright (c) 2020, Mike Wolfram
+ * Copyright (c) 2021, Raphael Lehmann
  *
  * This file is part of the modm project.
  *
@@ -46,8 +47,10 @@ public:
 	{
 		if constexpr (ID == 1)
 			Rcc::enable<Peripheral::Dma1>();
+%% if (dma.instance | length) > 1
 		else
 			Rcc::enable<Peripheral::Dma2>();
+%% endif
 	}
 	/**
 	 * Disable the DMA controller in the RCC
@@ -57,8 +60,10 @@ public:
 	{
 		if constexpr (ID == 1)
 			Rcc::disable<Peripheral::Dma1>();
+%% if (dma.instance | length) > 1
 		else
 			Rcc::disable<Peripheral::Dma2>();
+%% endif
 	}
 
 	/**
@@ -225,16 +230,22 @@ public:
 		{
 			transferComplete = irqHandler;
 		}
+
 		/**
 		 * Set the peripheral that operates the channel
 		 */
 		template <DmaBase::Request dmaRequest>
 		static void
 		setPeripheralRequest()
 		{
+%% if dmaType in ["stm32-channel-request"]
 			DMA_Request_TypeDef *DMA_REQ = reinterpret_cast<DMA_Request_TypeDef *>(ControlHal::DMA_CSEL);
 			DMA_REQ->CSELR &= ~(0x0f << (uint32_t(ChannelID) * 4));
 			DMA_REQ->CSELR |= uint32_t(dmaRequest) << (uint32_t(ChannelID) * 4);
+%% else
+			// Nothing to see here. This controller has no request mux, instead
+			// all requests are or-ed together.
+%% endif
 		}
 
 		/**
@@ -349,6 +360,7 @@ public:
  *     ...
  * };
  */
+%% if dmaType in ["stm32-channel-request"]
 %% for channels in dma["channels"]
 	%% for channel in channels.channel
 		%% for request in channel.request
@@ -357,7 +369,7 @@ public:
 				%% if signal.instance is defined
 					%% set peripheral = peripheral ~ signal.instance
 				%% else
-					%% if peripheral not in ["Quadspi", "Aes", "Dcmi"]
+					%% if peripheral in ["Dac", "Lpuart", "Swpmi"] and target["family"] not in ["f1", "f3", "l0", "l1"]
 						%% set peripheral = peripheral ~ 1
 					%% endif
 				%% endif
@@ -375,6 +387,32 @@ struct DmaController<{{ channels.instance }}>::Channel<DmaBase::Channel::Channel
 	%% endfor
 %% endfor
 
+%%else
+%% for channels in dma["channels"]
+	%% for channel in channels.channel
+		%% for signal in channel.signal
+			%% set peripheral = signal.driver.capitalize()
+			%% if signal.instance is defined
+				%% set peripheral = peripheral ~ signal.instance
+			%% else
+				%% if peripheral in ["Dac", "Lpuart", "Swpmi"] and target["family"] not in ["f1", "f3", "l0", "l1"]
+					%% set peripheral = peripheral ~ 1
+				%% endif
+			%% endif
+template <>
+template <>
+template <>
+struct DmaController<{{ channels.instance }}>::Channel<DmaBase::Channel::Channel{{ channel.position }}>::RequestMapping<Peripheral::{{ peripheral }}{% if signal.name is defined %}, DmaBase::Signal::{{ signal.name.capitalize() }}{% endif %}>
+{
+	using Channel = DmaController<{{ channels.instance }}>::Channel<DmaBase::Channel::Channel{{ channel.position }}>;
+	static constexpr DmaBase::Request Request = DmaBase::Request::Any;
+};
+
+		%% endfor
+	%% endfor
+%% endfor
+
+%%endif
 }	// namespace platform
 
 }	// namespace modm

src/modm/platform/dma/stm32/dma_base.hpp.in

@@ -2,6 +2,7 @@
  * Copyright (c) 2014, Kevin Läufer
  * Copyright (c) 2014-2017, Niklas Hauser
  * Copyright (c) 2020, Mike Wolfram
+ * Copyright (c) 2021, Raphael Lehmann
  *
  * This file is part of the modm project.
  *
@@ -15,6 +16,8 @@
 #define MODM_STM32_DMA_BASE_HPP
 
 #include <stdint.h>
+#include <cstddef>
+
 #include "../device.hpp"
 
 #include <modm/architecture/interface/assert.hpp>
@@ -23,7 +26,7 @@
 
 %% if target["family"] == "f4"
 	%% set reg_prefix = "DMA_SxCR"
-%% elif target["family"] in ["f3", "l4"]
+%% elif dmaType in ["stm32-channel-request", "stm32-channel"]
 	%% set reg_prefix = "DMA_CCR"
 %% endif
 
@@ -81,7 +84,7 @@ public:
 		Dma 		= 0,
 		Peripheral 	= DMA_SxCR_PFCTRL, ///< the peripheral is the flow controller
 	};
-%% elif target["family"] in ["f3", "l4"]
+%% elif dmaType in ["stm32-channel-request", "stm32-channel"]
 	%% set channel_count = namespace(max_channels = 0)
 	%% for controller in dmaController
 		%% if channel_count.max_channels < controller.channels
@@ -96,7 +99,7 @@ public:
 	%% endfor
 	};
 
-	%% if target["family"] == "l4"
+	%% if dmaType in ["stm32-channel-request"]
 	%% set request_count = namespace(max_requests = 0)
 	%% for channels in dma["channels"]
 		%% for channel in channels.channel
@@ -114,6 +117,14 @@ public:
 		Request{{ request }}{% if request == 0 %} = 0{% endif %},
 	%% endfor
 	};
+	%% else
+	enum class
+	Request
+	{
+		// Nothing to see here. This controller has no request mux, instead
+		// all requests are OR-ed together.
+		Any
+	};
 	%% endif
 %% endif
 
@@ -181,7 +192,7 @@ public:
 		MemoryToPeripheral 	= DMA_SxCR_DIR_0,
 		/// Source: DMA_SxPAR; Sink: DMA_SxM0AR
 		MemoryToMemory 		= DMA_SxCR_DIR_1,
-%% elif target["family"] in ["f3", "l4"]
+%% elif dmaType in ["stm32-channel-request", "stm32-channel"]
 		/// Source: DMA_CPARx; Sink: DMA_CMARx
 		PeripheralToMemory 	= 0,
 		/// Source: DMA_CMARx; Sink: DMA_CPARx
@@ -219,7 +230,7 @@ protected:
 			DMA_SxCR_PL_1    | DMA_SxCR_PL_0    |						// Priority
 			DMA_SxCR_CIRC    |											// CircularMode
 			DMA_SxCR_PFCTRL;											// FlowControl
-%% elif target["family"] in ["f3", "l4"]
+%% elif dmaType in ["stm32-channel-request", "stm32-channel"]
 	static constexpr uint32_t memoryMask =
 			DMA_CCR_MSIZE_0  | DMA_CCR_MSIZE_1  |	// MemoryDataSize
 			DMA_CCR_MINC                        |	// MemoryIncrementMode
@@ -248,13 +259,15 @@ protected:
 	struct Nvic;
 };
 
-%% for channels in dma["channels"]
+%% for instance, irqs in irqList.items()
 template <>
-struct DmaBase::Nvic<{{ channels.instance }}>
+struct DmaBase::Nvic<{{ instance }}>
 {
 	static constexpr IRQn_Type DmaIrqs[] {
-	%% for channel in channels.channel
-			DMA{{ channels.instance }}_Channel{{ channel.position }}_IRQn,
+	%% for channels in irqs
+	%% for i in range(channels | length)
+			DMA{{ instance }}_Channel{{ channels | join("_") }}_IRQn,
+	%% endfor
 	%% endfor
 	};
 };

src/modm/platform/dma/stm32/dma_hal.hpp.in

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020, Mike Wolfram
+ * Copyright (c) 2021, Raphael Lehmann
  *
  * This file is part of the modm project.
  *
@@ -22,6 +23,7 @@ namespace modm
 namespace platform
 {
 
+
 /**
  * Hardware abstraction of DMA controller
  *
@@ -45,20 +47,24 @@ class DmaHal : public DmaBase
 	static constexpr uint32_t getBaseAddress() {
 		if (id == 1)
 			return DMA1_BASE;
+%% if (dma.instance | length) > 1
 		else
 			return DMA2_BASE;
+%% endif
 	}
 	/**
-	 * Get the base address of the DMA channel reigsters
+	 * Get the base address of the DMA channel registers
 	 *
 	 * @tparam id The number of the DMA channel
 	 */
 	template <uint32_t id>
 	static constexpr uint32_t getChannelBaseAddress() {
 		if (id == 1)
 			return DMA1_Channel1_BASE;
+%% if (dma.instance | length) > 1
 		else
 			return DMA2_Channel1_BASE;
+%% endif
 	}
 	/**
 	 * Get the address of the channel selection register
@@ -67,10 +73,18 @@ class DmaHal : public DmaBase
 	 */
 	template <uint32_t id>
 	static constexpr uint32_t getCselAddress() {
+%% if dmaType in ["stm32-channel-request"]
 		if (id == 1)
 			return DMA1_CSELR_BASE;
+%% if (dma.instance | length) > 1
 		else
 			return DMA2_CSELR_BASE;
+%%endif
+%% else
+		// Nothing to see here. This controller has no request mux, instead
+		// all requests are OR-ed together.
+		return 0;
+%% endif
 	}
 
 public:

src/modm/platform/dma/stm32/dma_hal_impl.hpp.in

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020, Mike Wolfram
+ * Copyright (c) 2021, Raphael Lehmann
  *
  * This file is part of the modm project.
  *
@@ -23,7 +24,7 @@ modm::platform::DmaChannelHal<ChannelID, CHANNEL_BASE>::start()
 
 %% if target["family"] == "f4"
 	Base->CR |= DMA_SxCR_EN;
-%% else
+%% elif dmaType in ["stm32-channel-request", "stm32-channel"]
 	Base->CCR |= DMA_CCR_EN;
 %% endif
 }
@@ -37,7 +38,7 @@ modm::platform::DmaChannelHal<ChannelID, CHANNEL_BASE>::stop()
 %% if target["family"] == "f4"
 	Base->CR &= ~DMA_SxCR_EN;
 	while (Base->SCR & DMA_SxCR_EN); // wait for stream to be stopped
-%% else
+%% elif dmaType in ["stm32-channel-request", "stm32-channel"]
 	Base->CCR &= ~DMA_CCR_EN;
 	while (Base->CCR & DMA_CCR_EN); // wait for stream to be stopped
 %% endif
@@ -52,7 +53,7 @@ modm::platform::DmaChannelHal<ChannelID, CHANNEL_BASE>::getDataTransferDirection
 	return static_cast<DataTransferDirection>(
 %% if target["family"] == "f4"
 		Base->CR & (DMA_SxCR_DIR_0 | DMA_SxCR_DIR_1));
-%% else
+%% elif dmaType in ["stm32-channel-request", "stm32-channel"]
 		Base->CCR & (DMA_CCR_MEM2MEM | DMA_CCR_DIR));
 %% endif
 }