[stm32] Port ADC driver to STM32L5

Author: chris-durand

src/modm/platform/adc/stm32f3/adc.hpp.in

@@ -62,12 +62,16 @@ public:
 %% elif target["family"] in ["l4", "g4"]
 		Temperature = 17,
 		BatDiv3     = 18,
+%% elif target["family"] in ["l5"]
+		InternalReference = 0,
+		Temperature = 17,
+		BatDiv3     = 18,
 %% endif
 %% elif id == 2
 %% if target["family"] in ["f3"]
 		Opamp2 = 17,
 		InternalReference = 18,
-%% elif target["family"] in ["l4", "g4"]
+%% elif target["family"] in ["l4", "l5", "g4"]
 		Dac1 = 17,
 		Dac2 = 18,
 %% endif
@@ -107,16 +111,18 @@ public:
 		NoClock = 0, // No clock selected.
 %% if target["family"] in ["g4"]
 %% if id in [1, 2]
-		Pll = RCC_CCIPR_ADC12SEL_0, // PLL “P” clock selected as ADC clock
-		SystemClock = RCC_CCIPR_ADC12SEL_1 , // System clock selected as ADCs clock
+		Pll = RCC_{{ ccipr }}_ADC12SEL_0, // PLL “P” clock selected as ADC clock
+		SystemClock = RCC_{{ ccipr }}_ADC12SEL_1 , // System clock selected as ADCs clock
 %% elif id in [3, 4, 5]
-		Pll = RCC_CCIPR_ADC345SEL_0, // PLL “P” clock selected as ADC clock
-		SystemClock = RCC_CCIPR_ADC345SEL_1 , // System clock selected as ADCs clock
+		Pll = RCC_{{ ccipr }}_ADC345SEL_0, // PLL “P” clock selected as ADC clock
+		SystemClock = RCC_{{ ccipr }}_ADC345SEL_1 , // System clock selected as ADCs clock
 %% endif
 %% else
-		PllSai1 = RCC_CCIPR_ADCSEL_0, // PLLSAI1 "R" clock (PLLADC1CLK) selected as ADCs clock
-		PllSai2 = RCC_CCIPR_ADCSEL_1, // PLLSAI2 "R" clock (PLLADC2CLK) selected as ADCs clock
-		SystemClock = RCC_CCIPR_ADCSEL_1 | RCC_CCIPR_ADCSEL_0, // System clock selected as ADCs clock
+		PllSai1 = RCC_{{ ccipr }}_ADCSEL_0, // PLLSAI1 "R" clock (PLLADC1CLK) selected as ADCs clock
+%% if target["family"] != "l5"
+		PllSai2 = RCC_{{ ccipr }}_ADCSEL_1, // PLLSAI2 "R" clock (PLLADC2CLK) selected as ADCs clock
+%% endif
+		SystemClock = RCC_{{ ccipr }}_ADCSEL_1 | RCC_{{ ccipr }}_ADCSEL_0, // System clock selected as ADCs clock
 %% endif
 	};
 %% endif
@@ -139,7 +145,7 @@ public:
 		Div128 				= RCC_CFGR2_{{ adc_pre }}_DIV128,
 		Div256 				= RCC_CFGR2_{{ adc_pre }}_DIV256,
 		Div256AllBits 		= RCC_CFGR2_{{ adc_pre }},	// for bit clear
-%% elif target["family"] in ["l4", "g4"]
+%% elif target["family"] in ["l4", "l5", "g4"]
 		Div1 				= 0,
 		Div2 				= ADC_CCR_PRESC_0,
 		Div4 				= ADC_CCR_PRESC_1,
@@ -156,7 +162,7 @@ public:
 %% endif
 	};
 
-%% if target["family"] in ["l4", "g4"]
+%% if target["family"] in ["l4", "l5", "g4"]
 	enum class SampleTime : uint8_t	// TODO: What is the best type?
 	{
 		Cycles2 	= 0b000,	//!   1.5 ADC clock cycles
@@ -190,7 +196,7 @@ public:
 
 	enum class VoltageRegulatorState : uint32_t
 	{
-%% if target["family"] in ["l4", "g4"]
+%% if target["family"] in ["l4", "l5", "g4"]
 		Enabled 		= ADC_CR_ADVREGEN,
 %% elif target["family"] in ["f3"]
 		// Intermediate state is needed to move from enabled to disabled

src/modm/platform/adc/stm32f3/adc_impl.hpp.in

@@ -29,18 +29,18 @@ modm::platform::Adc{{ id }}::initialize(const ClockMode clk,
 	uint32_t tmp = 0;
 
 	// enable clock
-%% if target["family"] in ["f3", "g4"]
+%% if target["family"] in ["f3", "g4", "l5"]
 	RCC->{{ ahb }}ENR |= RCC_{{ ahb }}ENR_ADC{{ id_common }}EN;
 %% elif target["family"] in ["l4"]
 	Rcc::enable<Peripheral::Adc1>();
 %% endif
 
 %% if clock_mux
 	// select clock source
-	RCC->CCIPR |= static_cast<uint32_t>(clk_src);
+	RCC->{{ ccipr }} |= static_cast<uint32_t>(clk_src);
 %% endif
 
-%% if target["family"] in ["l4", "g4"]
+%% if target["family"] in ["l4", "l5", "g4"]
 	// Disable deep power down
 	ADC{{ id }}->CR &= ~ADC_CR_DEEPPWD;
 %% endif
@@ -90,7 +90,7 @@ modm::platform::Adc{{ id }}::disable(const bool blocking)
 		while(ADC{{ id }}->CR & ADC_CR_ADDIS);
 	}
 	// disable clock
-%% if target["family"] in ["f3", "g4"]
+%% if target["family"] in ["f3", "g4", "l5"]
 	RCC->{{ ahb }}ENR &= ~RCC_{{ ahb }}ENR_ADC{{ id_common }}EN;
 %% elif target["family"] in ["l4"]
 	Rcc::disable<Peripheral::Adc1>();
@@ -106,7 +106,7 @@ modm::platform::Adc{{ id }}::setPrescaler(const Prescaler pre)
 	tmp &= ~static_cast<uint32_t>(Prescaler::Div256AllBits);
 	tmp |=  static_cast<uint32_t>(pre);
 	RCC->CFGR2 = tmp;
-%% elif target["family"] in ["l4", "g4"]
+%% elif target["family"] in ["l4", "l5", "g4"]
 	tmp  = ADC{{ id_common_u }}->CCR;
 	tmp &= ~static_cast<uint32_t>(Prescaler::Div256AllBits);
 	tmp |=  static_cast<uint32_t>(pre);

src/modm/platform/adc/stm32f3/module.lb

@@ -36,7 +36,7 @@ class Instance(Module):
             if target["family"] == "f3":
                 # 13-14 reserved
                 channels = [1,2,3,4,5,6,7,8,9,10,11,12,15,16,17,18]
-            elif target["family"] == "l4":
+            elif target["family"] in ["l4", "l5"]:
                 # ADC1 is connected to 16 external channels + 3 internal channels
                 channels = range(1,17)
             elif target["family"] == "g4":
@@ -52,6 +52,9 @@ class Instance(Module):
             elif target["family"] == "g4":
                 # ADC2 is connected to 16 external channels + 2 internal channels
                 channels = range(1,17)
+            elif target["family"] == "l5":
+                # ADC1 is connected to 16 external channels + 2 internal channels
+                channels = range(1,17)
             else:
                 # ADC2 is connected to 16 external channels + 2 internal channels
                 channels = range(1,17)
@@ -99,6 +102,7 @@ class Instance(Module):
             properties["clock_mux"] = False
         elif target["family"] == "l4":
             properties["adc_ccr"] = "ADC_CCR"
+            properties["ccipr"] = "CCIPR"
             if len(driver["instance"]) == 1 and "q5a" not in target.string:
                 properties["id_common"] = "1"
                 properties["id_common_u"] = "1_COMMON"
@@ -109,9 +113,17 @@ class Instance(Module):
                 properties["id_common"] = "123"
                 properties["id_common_u"] = "123_COMMON"
             properties["clock_mux"] = (target["name"] not in ("12", "22"))
+        elif target["family"] == "l5":
+            properties["adc_ccr"] = "ADC_CCR"
+            properties["ccipr"] = "CCIPR1"
+            properties["ahb"] = "AHB2"
+            properties["id_common"] = ""
+            properties["id_common_u"] = "12_COMMON"
+            properties["clock_mux"] = True
         elif target["family"] == "g4":
             properties["ahb"] = "AHB2"
             properties["adc_ccr"] = "ADC_CCR"
+            properties["ccipr"] = "CCIPR"
             if instance_id in [1, 2]:
                 properties["id_common"] = "12"
                 properties["id_common_u"] = "12_COMMON"