[I2S] Add pin configuration for I2S DAC

Remove not used parameter from I2S PLL initializer function.

Pin setup for the I2S DAC can be done
by calling Board::initializeCs43()

Author: ledneczki

src/modm/board/disco_f407vg/board.hpp

@@ -92,7 +92,7 @@ struct SystemClock {
 			.pllN = 258,	// 1 MHz * N=258 -> 258 MHz
 			.pllR = 3		// 258 MHz / R=3 -> 86 MHz
 		};
-		Rcc::enablePllI2s(Rcc::PllSource::ExternalCrystal, pllI2sFactors, 2048);
+		Rcc::enablePllI2s(pllI2sFactors, 2048);
 		// set flash latency for 168MHz
 		Rcc::setFlashLatency<Frequency>();
 		// switch system clock to PLL output
@@ -148,7 +148,7 @@ using Scl = GpioB6;			// Audio_SCL
 using Sda = GpioB9;			// Audio_SDA
 
 using I2cMaster = I2cMaster1;
-//using I2sMaster = I2sMaster3;
+using I2sMaster = I2sMaster3;
 }
 
 
@@ -200,10 +200,8 @@ initializeLis3()
 inline void
 initializeCs43()
 {
-//	cs43::Lrck::connect(cs43::I2sMaster::Ws);
-//	cs43::Mclk::connect(cs43::I2sMaster::Mck);
-//	cs43::Sclk::connect(cs43::I2sMaster::Ck);
-//	cs43::Sdin::connect(cs43::I2sMaster::Sd);
+	cs43::I2sMaster::connect<cs43::Mclk::Mck, cs43::Sclk::Ck,
+							cs43::Lrck::Ws, cs43::Sdin::Sd>();
 
 	cs43::Reset::setOutput(modm::Gpio::High);
 

src/modm/platform/clock/stm32/rcc.cpp.in

@@ -307,7 +307,7 @@ Rcc::enablePll{{id}}(PllSource source, const PllFactors& pllFactors, uint32_t wa
 
 %% if plli2s
 bool
-modm::platform::Rcc::enablePllI2s(PllSource, const PllI2sFactors& pllFactors, uint32_t waitCycles)
+modm::platform::Rcc::enablePllI2s(const PllI2sFactors& pllFactors, uint32_t waitCycles)
 {
 	// Read reserved and don't care values and clear all other values
 	uint32_t tmp = RCC->PLLI2SCFGR & ~(RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR);

src/modm/platform/clock/stm32/rcc.hpp.in

@@ -611,18 +611,25 @@ public:
 
 %% if target["family"] == "f4"
 	/** TODO: comments
+	 * \code
 	 * input clock is the HSE or HSI divided by M
 	 * f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)
 	 * f(PLL I2S clock output) = f(VCO clock) / PLLI2SR
+	 * \endcode
+	 * 
 	 * 
 	 * \param	pllN
-	 * PLLI2S multiplication factor for VCO
-	 * 50 <= PLLI2SN <= 432
+	 *	 	PLLI2S multiplication factor for VCO
+	 *	 	Caution: The software has to set these bits correctly
+	 *	 		to ensure that the VCO output frequency
+	 * 			is between 100 and 432 MHz. 
+	 *  	50 <= PLLI2SN <= 432
 	 * 
 	 * \param	pllR
-	 * PLLI2S division factor for I2S clocks
-	 * Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.
-	 * 2 <= PLLR <= 7
+	 * 		PLLI2S division factor for I2S clocks
+	 * 		Caution: The I2Ss requires a frequency lower than
+	 * 			or equal to 192 MHz to work correctly.
+	 * 		2 <= PLLR <= 7
 	 */
 	struct PllI2sFactors
 	{
@@ -632,7 +639,7 @@ public:
 
 	/* TODO: comments */
 	static bool
-	enablePllI2s(PllSource, const PllI2sFactors& pllFactors, uint32_t waitCycles);
+	enablePllI2s(const PllI2sFactors& pllFactors, uint32_t waitCycles);
 %% endif
 
 	// sinks