[stm32] Fix hang during F3/G4/L3 adc initialization for slow ADC clocks

Setting ADC_CR_ADEN after calibration is only possible after 4 ADC clock
cycles have elapsed. In case the ADC clock is much slower than the CPU
clock that flag was never set and the initialization blocked infinitely
waiting for the ready flag to get set.

Author: chris-durand

src/modm/platform/adc/stm32f3/adc_impl.hpp.in

@@ -65,14 +65,18 @@ modm::platform::Adc{{ id }}::initialize(const ClockMode clk,
 	ADC{{ id }}->CR |= static_cast<uint32_t>(VoltageRegulatorState::Enabled);
 	modm::delay_us(10);	// FIXME: this is ugly -> find better solution
 
-	// Clear ready flag
-	ADC{{ id }}->ISR |= ADC_ISR_ADRDY;
+	acknowledgeInterruptFlag(InterruptFlag::Ready);
 
 	calibrate(cal, true);	// blocking calibration
 
 	ADC{{ id }}->CR |= ADC_CR_ADEN;
 	if (blocking) {
-		while(not isReady());
+		// ADEN can only be set 4 ADC clock cycles after ADC_CR_ADCAL gets
+		// cleared. Setting it in a loop ensures the flag gets set for ADC
+		// clocks slower than the CPU clock.
+		while (not isReady()) {
+			ADC{{ id }}->CR |= ADC_CR_ADEN;
+		}
 		acknowledgeInterruptFlag(InterruptFlag::Ready);
 	}
 }