[sam] Add PCK configuration to PMC driver and fix enableUPll()

Co-authored-by: Raphael Lehmann <[email protected]>

Author: chris-durand

src/modm/platform/clock/sam_pmc/clockgen.cpp.in

@@ -11,6 +11,7 @@
 // ----------------------------------------------------------------------------
 
 #include "clockgen.hpp"
+#include <algorithm>
 #include <cmath>
 
 // CMSIS Core compliance
@@ -135,4 +136,31 @@ ClockGen::pllBFrequency()
 }
 %% endif
 
+%% if target.family == "e7x/s7x/v7x"
+void
+ClockGen::enablePck(Pck clock)
+{
+	PMC->PMC_SCER = 1u << (PMC_SCER_PCK0_Pos + static_cast<uint8_t>(clock));
+
+	int_fast16_t deadlockPreventer = 10'000;  // max ~10ms
+	const uint8_t pckrdyPos = PMC_SR_PCKRDY0_Pos + static_cast<uint8_t>(clock);
+	while (((PMC->PMC_SR & (1 << pckrdyPos)) == 0) and (deadlockPreventer-- > 0))
+		modm::delay(std::chrono::microseconds{1});
+	modm_assert(deadlockPreventer > 0, "clockgen.pck.enable", "timeout expired");
+}
+
+void
+ClockGen::disablePck(Pck clock)
+{
+	PMC->PMC_SCDR = 1u << (PMC_SCDR_PCK0_Pos + static_cast<uint8_t>(clock));
+}
+
+void
+ClockGen::configurePck(Pck clock, PckSource source, uint16_t divider)
+{
+	PMC->PMC_PCK[uint8_t(clock)] = PMC_PCK_CSS(uint8_t(source)) |
+		PMC_PCK_PRES(std::clamp<uint16_t>(divider, 1, 256) - 1);
+}
+%% endif
+
 } // namespace modm::platform

src/modm/platform/clock/sam_pmc/clockgen.hpp.in

@@ -228,6 +228,32 @@ UtmiRefClk : uint32_t
 %% endif
 
 static constexpr uint32_t SlowClkFreqHz = 32'768;
+
+%% if target.family == "e7x/s7x/v7x"
+/// Programmable clocks
+enum class Pck
+{
+	Pck0 = 0,
+	Pck1 = 1,
+	Pck2 = 2,
+	Pck3 = 3,
+	Pck4 = 4,
+	Pck5 = 5,
+	Pck6 = 6,
+	Pck7 = 7
+};
+
+/// Programmable clock sources
+enum class PckSource
+{
+	SlowClock = PMC_PCK_CSS_SLOW_CLK,
+	MainClock = PMC_PCK_CSS_MAIN_CLK,
+	PllA = PMC_PCK_CSS_PLLA_CLK,
+	UPll = PMC_PCK_CSS_UPLL_CLK,
+	Mck = PMC_PCK_CSS_MCK
+};
+%% endif
+
 /// @}
 
 /**
@@ -295,6 +321,20 @@ public:
 	template<UtmiRefClk refclk>
 	static void
 	enableUPll(uint32_t wait_cycles = 50);
+
+	static void
+	enablePck(Pck clock);
+
+	static void
+	disablePck(Pck clock);
+
+	/**
+	 * Configure programmable clock.
+	 * @warning The clock must be disabled when changing configuration.
+	 * @param divider clock divider (1-256)
+	 */
+	static void
+	configurePck(Pck clock, PckSource source, uint16_t divider);
 %% endif
 
 	template <MasterClkSource src, MasterClkPrescaler pres,

src/modm/platform/clock/sam_pmc/clockgen_impl.hpp.in

@@ -169,7 +169,7 @@ template<UtmiRefClk refclk>
 void
 ClockGen::enableUPll(uint32_t wait_cycles)
 {
-	REG_UTMI_CKTRIM = refclk;
+	UTMI->UTMI_CKTRIM = static_cast<uint32_t>(refclk);
 	PMC->CKGR_UCKR =
 		CKGR_UCKR_UPLLCOUNT(wait_cycles) |
 		CKGR_UCKR_UPLLEN;