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1 | 1 | /*
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2 | 2 | * Copyright (c) 2016, Sascha Schade
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3 | 3 | * Copyright (c) 2016-2017, Fabian Greif
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4 |
| - * Copyright (c) 2016-2017, 2019, Niklas Hauser |
| 4 | + * Copyright (c) 2016-2017, 2019, 2024, Niklas Hauser |
5 | 5 | * Copyright (c) 2021, Raphael Lehmann
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6 | 6 | * Copyright (c) 2021, Christopher Durand
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7 | 7 | *
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@@ -30,60 +30,75 @@ __modm_initialize_platform(void)
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30 | 30 | {
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31 | 31 | // Enable SYSCFG
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32 | 32 | %% if target.family in ["c0", "g0"]
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33 |
| - RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN; |
| 33 | + RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN; __DSB(); |
| 34 | +%% elif target.family == "f0" |
| 35 | + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; __DSB(); |
34 | 36 | %% elif target.family == "f1"
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35 |
| - RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; |
| 37 | + RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; __DSB(); |
36 | 38 | %% elif target.family == "h7"
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37 |
| - RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; |
| 39 | + RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; __DSB(); |
38 | 40 | %% elif target.family == "u5"
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39 |
| - RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; |
| 41 | + RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; __DSB(); |
40 | 42 | %% else
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41 |
| - RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; |
| 43 | + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; __DSB(); |
42 | 44 | %% endif
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43 | 45 |
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44 |
| -%% if target.family == "f4" |
45 |
| -// Only the more powerful F4 targets have CCM or Backup SRAM |
46 |
| -#ifdef RCC_AHB1ENR_CCMDATARAMEN |
47 | 46 | // Enable power to backup domain
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48 |
| - RCC->APB1ENR |= RCC_APB1ENR_PWREN; |
49 |
| - // Enable write access to backup SRAM |
| 47 | +%% if target.family == "f1" |
| 48 | + RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN; __DSB(); |
| 49 | +%% elif target.family in ["f0", "f2", "f3", "f4", "f7", "l0", "l1"] |
| 50 | + RCC->APB1ENR |= RCC_APB1ENR_PWREN; __DSB(); |
| 51 | +%% elif target.family in ["c0", "g0", "u0"] |
| 52 | + RCC->APBENR1 |= RCC_APBENR1_PWREN; __DSB(); |
| 53 | +%% elif target.family in ["g4", "l4", "l5"] |
| 54 | + RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN; __DSB(); |
| 55 | +%% elif target.family == "u5" |
| 56 | + RCC->AHB3ENR |= RCC_AHB3ENR_PWREN; __DSB(); |
| 57 | +%% endif |
| 58 | + |
| 59 | +%% if target.family in ["f0", "f1", "f2", "f3", "f4", "l0", "l1"] |
50 | 60 | PWR->CR |= PWR_CR_DBP;
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| 61 | +%% elif target.family in ["f7", "g0", "g4", "h7", "l4", "l5", "u0", "wb", "wl"] |
| 62 | + PWR->CR1 |= PWR_CR1_DBP; |
| 63 | +%% elif target.family == "h5" |
| 64 | + PWR->DBPCR |= PWR_DBPCR_DBP; |
| 65 | +%% elif target.family in ["u5", "wba"] |
| 66 | + PWR->DBPR |= PWR_DBPR_DBP; |
| 67 | +%% endif |
| 68 | + |
| 69 | +%% if target.family == "f4" |
| 70 | + // Only the more powerful F4 targets have CCM or Backup SRAM |
| 71 | +#ifdef RCC_AHB1ENR_CCMDATARAMEN |
51 | 72 | // Enable Core Coupled Memory (CCM) and backup SRAM (BKPSRAM)
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52 | 73 | RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN | RCC_AHB1ENR_BKPSRAMEN;
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53 | 74 | #endif
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54 | 75 | %% elif target.family == "f7"
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55 | 76 | // Reset from DFU settings to reset values.
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56 | 77 | RCC->DCKCFGR2 = 0;
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57 |
| - // Enable power to backup domain |
58 |
| - RCC->APB1ENR |= RCC_APB1ENR_PWREN; |
59 |
| - // Enable write access to backup SRAM |
60 |
| - PWR->CR1 |= PWR_CR1_DBP; |
61 | 78 | // Enable Data Tighly Coupled Memory (DTCM) and backup SRAM (BKPSRAM)
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62 | 79 | RCC->AHB1ENR |= RCC_AHB1ENR_DTCMRAMEN | RCC_AHB1ENR_BKPSRAMEN;
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63 |
| -%% elif target.family in ["g0", "g4", "l4", "l5"] |
64 |
| -%% if target.family in ["l4", "g4"] |
65 |
| - RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN; |
66 |
| -%% elif target.family != "g0" |
67 |
| -#ifdef PWR_CR2_IOSV |
68 |
| - RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN; |
69 |
| -#endif |
70 |
| -%% endif |
71 |
| - |
| 80 | +%% elif target.family == "h7" |
| 81 | + // Enable all SRAMs |
| 82 | + %% if target.name[0].isnumeric() |
| 83 | + RCC->AHB2ENR |= RCC_AHB2ENR_SRAM1EN | RCC_AHB2ENR_SRAM2EN; |
| 84 | + %% else |
| 85 | + RCC->AHB2ENR |= RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN; |
| 86 | + %% endif |
| 87 | + RCC->AHB4ENR |= RCC_AHB4ENR_BKPRAMEN; |
| 88 | +%% elif target.family in ["g4", "l4", "l5"] |
72 | 89 | #ifdef PWR_CR2_IOSV
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73 | 90 | // Enable VDDIO2
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74 | 91 | PWR->CR2 |= PWR_CR2_IOSV;
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75 | 92 | #endif
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76 |
| -%% elif target.family in ["u5"] |
77 |
| - RCC->AHB3ENR |= RCC_AHB3ENR_PWREN; |
| 93 | +%% elif target.family == "u5" |
78 | 94 | // Enable power for VDDIO2 and USB
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79 | 95 | PWR->SVMCR |= PWR_SVMCR_ASV | PWR_SVMCR_IO2SV | PWR_SVMCR_USV;
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80 |
| - |
81 | 96 | // Enable Backup SRAM (BKPSRAM)
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82 |
| - PWR->DBPR |= PWR_DBPR_DBP; |
83 | 97 | RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
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84 | 98 | %% endif
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85 | 99 |
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86 | 100 | %% if vector_table_location == "ram"
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| 101 | + __DSB(); |
87 | 102 | // Remap SRAM to 0x0 for vector table relocation without VTOR register
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88 | 103 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE;
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89 | 104 | %% endif
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