[delay] Fix register constraints for subs.n instruction

Author: salkinium

src/modm/platform/core/cortex/delay_impl.hpp.in

@@ -33,15 +33,16 @@ extern uint16_t delay_fcpu_MHz;
 
 inline void modm_fastcode delay_ns(uint32_t ns)
 {
-	volatile uint32_t overhead_cycles;
+	volatile uint32_t cycles;
 	// ns_per_loop = nanoseconds per cycle times cycles per loop ({{loop}} cycles)
 	asm volatile (
-		".syntax unified"       "\n\t"
-		"muls.n	%0, %0, %2"     "\n\t"  // multiply the overhead cycles with the ns per cycle:  1-2 cycles on cm3, up to 32 cycles on cm0
-		"subs.n	%1, %1, %0"     "\n\t"  // subtract the overhead in ns from the input:          1 cycle
-	"1:  subs.n	%1, %1, %2"     "\n\t"  // subtract the ns per loop from the input:             1 cycle
-		"bpl.n	1b"             "\n\t"  // keep doing that while result is still positive:      2 cycles (when taken)
-	: "=r" (overhead_cycles) : "r" (ns), "r" (platform::delay_ns_per_loop), "0" ({{ (overhead / loop) | int}}));
+		".syntax unified \n\t"
+		".align 4 \n\t"
+		"muls.n	%[cyc], %[cyc], %[dnpl] \n\t"	// multiply the overhead cycles with the ns per cycle:  1-2 cycles on cm3, up to 32 cycles on cm0
+		"subs.n	%[cyc], %[cyc], %[ovhd] \n\t"	// subtract the overhead in ns from the input:          1 cycle
+	"1:  subs.n	%[cyc], %[cyc], %[dnpl] \n\t"	// subtract the ns per loop from the input:             1 cycle
+		"bpl.n	1b"								// keep doing that while result is still positive:      2 cycles (when taken)
+	: [cyc] "=l" (cycles) : "0" (ns), [dnpl] "l" (platform::delay_ns_per_loop), [ovhd] "l" ({{(overhead / loop) | int}}));
 	// => loop is {{loop}} cycles long
 }
 void delay_us(uint32_t us);