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andryblacksalkinium
andryblack
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salkinium
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[rp] Add DMA module
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‎src/modm/platform/dma/rp/dma.hpp.in

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/*
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* Copyright (c) 2022, Andrey Kunitsyn
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*
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* This file is part of the modm project.
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/.
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*/
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// ----------------------------------------------------------------------------
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#pragma once
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#include <cstdint>
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#include <algorithm>
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#include "../device.hpp"
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#include <hardware/structs/dma.h>
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#include <hardware/regs/dreq.h>
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namespace modm::platform
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{
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/// @ingroup modm_platform_dma
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struct DmaBase
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{
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using IrqHandler = void (*)(void);
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enum class Channel : uint32_t
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{
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%% for channel in dma.channel
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Channel{{channel.name}},
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%% endfor
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};
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enum class Request : uint32_t
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{
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Pio0_Tx0 = DREQ_PIO0_TX0,
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Pio0_Tx1 = DREQ_PIO0_TX1,
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Pio0_Tx2 = DREQ_PIO0_TX2,
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Pio0_Tx3 = DREQ_PIO0_TX3,
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Pio0_Rx0 = DREQ_PIO0_RX0,
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Pio0_Rx1 = DREQ_PIO0_RX1,
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Pio0_Rx2 = DREQ_PIO0_RX2,
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Pio0_Rx3 = DREQ_PIO0_RX3,
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Pio1_Tx0 = DREQ_PIO1_TX0,
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Pio1_Tx1 = DREQ_PIO1_TX1,
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Pio1_Tx2 = DREQ_PIO1_TX2,
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Pio1_Tx3 = DREQ_PIO1_TX3,
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Pio1_Rx0 = DREQ_PIO1_RX0,
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Pio1_Rx1 = DREQ_PIO1_RX1,
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Pio1_Rx2 = DREQ_PIO1_RX2,
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Pio1_Rx3 = DREQ_PIO1_RX3,
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Spi0_Tx = DREQ_SPI0_TX,
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Spi0_Rx = DREQ_SPI0_RX,
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Spi1_Tx = DREQ_SPI1_TX,
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Spi1_Rx = DREQ_SPI1_RX,
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Uart0_Tx = DREQ_UART0_TX,
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Uart0_Rx = DREQ_UART0_RX,
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Uart1_Tx = DREQ_UART1_TX,
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Uart1_Rx = DREQ_UART1_RX,
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Pwm_Wrap0 = DREQ_PWM_WRAP0,
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Pwm_Wrap1 = DREQ_PWM_WRAP1,
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Pwm_Wrap2 = DREQ_PWM_WRAP2,
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Pwm_Wrap3 = DREQ_PWM_WRAP3,
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Pwm_Wrap4 = DREQ_PWM_WRAP4,
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Pwm_Wrap5 = DREQ_PWM_WRAP5,
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Pwm_Wrap6 = DREQ_PWM_WRAP6,
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Pwm_Wrap7 = DREQ_PWM_WRAP7,
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I2c0_Tx = DREQ_I2C0_TX,
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I2c0_Rx = DREQ_I2C0_RX,
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I2c1_Tx = DREQ_I2C1_TX,
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I2c1_Rx = DREQ_I2C1_RX,
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Adc = DREQ_ADC,
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Xip_Stream = DREQ_XIP_STREAM,
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Xip_SsiTx = DREQ_XIP_SSITX,
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Xip_SsiRx = DREQ_XIP_SSIRX,
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Dma_Timer0 = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0,
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Dma_Timer1 = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1,
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Dma_Timer2 = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2,
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Dma_Timer3 = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3,
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Force = DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT,
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};
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enum class
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TransferDataSize : uint32_t
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{
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Byte = 0,
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Bit8 = Byte,
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HalfWord = 1,
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Bit16 = HalfWord,
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Word = 2,
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Bit32 = Word,
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};
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enum class
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Priority : uint32_t
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{
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Normal = 0,
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High = 1,
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};
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};
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/// @author Andrey Kunitsyn
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/// @ingroup modm_platform_dma
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class DmaController : public DmaBase
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{
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public:
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/**
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* Start multiple channels simultaneously
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*/
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template <class... Channels>
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static inline void start() {
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dma_hw->multi_channel_trigger = (Channels::mask | ...);
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}
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class ChannelDummy
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{
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public:
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static constexpr uint32_t mask = 0;
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static void
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configure(TransferDataSize transferDataSize,
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bool readIncrement,
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bool writeIncrement) {
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(void)transferDataSize;
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(void)readIncrement;
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(void)writeIncrement;
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}
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static void
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start() {}
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static void
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setReadAddress(uintptr_t address) {
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(void)address;
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}
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static void
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setWriteAddress(uintptr_t address) {
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(void)address;
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}
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static void
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setReadIncrementMode(bool increment) {
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(void)increment;
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}
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static void
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setWriteIncrementMode(bool increment) {
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(void)increment;
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}
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static void
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setDataLength(std::size_t length) {
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(void)length;
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}
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template <Request dmaRequest>
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static void
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setPeripheralRequest() {}
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static bool isBusy() { return false; }
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};
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/// Class representing a DMA channel/stream
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template <DmaBase::Channel ChannelID>
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class Channel
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{
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public:
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static constexpr DmaBase::Channel name = ChannelID;
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static constexpr uint32_t idx = uint32_t(ChannelID);
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static constexpr uint32_t mask = (1u << idx);
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/**
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* Configure the DMA channel
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*
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* Stops the DMA channel and writes the new values to its control register.
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*
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* @param[in] transferDataSize Size of data in transfer (byte, halfword, word)
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* @param[in] readIncrement Defines whether the read address is incremented
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* after a transfer completed
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* @param[in] writeIncrement Defines whether the write address is
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* incremented after a transfer completed
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*/
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static void
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configure(TransferDataSize transferDataSize, bool readIncrement, bool writeIncrement)
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{
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const uint32_t ctrl =
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(uint32_t(transferDataSize) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB) |
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(readIncrement ? DMA_CH0_CTRL_TRIG_INCR_READ_BITS : 0) |
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(writeIncrement ? DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS : 0) |
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(idx << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB) |
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DMA_CH0_CTRL_TRIG_EN_BITS |
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DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS;
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// write to alt1, dnt start
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dma_hw->ch[idx].al1_ctrl = ctrl;
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}
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/// Start the transfer of the DMA channel
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static void
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start()
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{
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dma_hw->multi_channel_trigger = mask;
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}
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/// Stop a DMA channel transfer
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static void
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stop()
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{
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dma_hw->abort = mask;
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while (dma_hw->abort & mask) __NOP();
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}
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/**
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* Set the read address of the DMA channel
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*
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* @note In Mem2Mem mode use this method to set the memory source address.
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*
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* @param[in] address Source address
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*/
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static void
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setReadAddress(uintptr_t address)
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{
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dma_hw->ch[idx].read_addr = address;
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}
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/**
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* Set the write address of the DMA channel
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*
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* @note In Mem2Mem mode use this method to set the memory destination address.
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*
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* @param[in] address Destination address
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*/
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static void
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setWriteAddress(uintptr_t address)
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{
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dma_hw->ch[idx].write_addr = address;
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}
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/**
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* Enable/disable read increment
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*
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* When enabled, the read address is incremented by the size of the data
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* (e.g. 1 for byte transfers, 4 for word transfers) after the transfer
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* completed.
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*
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* @param[in] increment Enable/disable
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*/
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static void
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setReadIncrementMode(bool increment)
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{
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if (increment) {
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hw_set_bits(&dma_hw->ch[idx].al1_ctrl,DMA_CH0_CTRL_TRIG_INCR_READ_BITS);
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} else {
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hw_clear_bits(&dma_hw->ch[idx].al1_ctrl,DMA_CH0_CTRL_TRIG_INCR_READ_BITS);
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}
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}
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/**
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* Enable/disable write increment
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*
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* When enabled, the write address is incremented by the size of the data
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* (e.g. 1 for byte transfers, 4 for word transfers) after the transfer
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* completed.
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*
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* @param[in] increment Enable/disable
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*/
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static void
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setWriteIncrementMode(bool increment)
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{
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if (increment) {
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hw_set_bits(&dma_hw->ch[idx].al1_ctrl,DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS);
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} else {
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hw_clear_bits(&dma_hw->ch[idx].al1_ctrl,DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS);
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}
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}
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/// Set the length of data to be transfered (num transactions, not bytes)
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static void
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setDataLength(std::size_t length)
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{
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dma_hw->ch[idx].transfer_count = length;
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}
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/// Set the peripheral that operates the channel
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template <Request dmaRequest>
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static void
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setPeripheralRequest()
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{
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hw_write_masked(&dma_hw->ch[idx].al1_ctrl,
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(uint32_t(dmaRequest) << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB),
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DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS);
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}
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/// Enable the specified interrupt of the channel
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static void
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enableInterrupt()
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{
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hw_clear_bits(&dma_hw->ch[idx].al1_ctrl,DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS);
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}
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/// Disable the specified interrupt of the channel
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static void
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disableInterrupt()
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{
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hw_set_bits(&dma_hw->ch[idx].al1_ctrl,DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS);
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}
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static inline bool isBusy()
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{
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return dma_hw->ch[idx].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS;
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}
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static inline bool isCompleted()
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{
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return !isBusy();
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}
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static inline void startWrite(const void* src,std::size_t count)
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{
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dma_hw->ch[idx].read_addr = (uint32_t)src;
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dma_hw->ch[idx].al1_transfer_count_trig = count;
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}
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static inline void startRead(void* dst,std::size_t count)
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{
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dma_hw->ch[idx].write_addr = (uint32_t)dst;
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dma_hw->ch[idx].al1_transfer_count_trig = count;
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}
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template <class OtherChannel>
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static inline void chainTo()
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{
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hw_write_masked(&dma_hw->ch[idx].al1_ctrl,
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(OtherChannel::idx << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB),
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DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS);
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}
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};
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};
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/**
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* Derive DMA controller classes for convenience. Every derived class defines
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* the channels available on that controller.
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* @ingroup modm_platform_dma
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*/
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class Dma: public DmaController
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{
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public:
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%% for channel in dma.channel
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using Channel{{ channel.name }} = DmaController::Channel<DmaBase::Channel::Channel{{ channel.name }}>;
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%% endfor
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};
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} // namespace modm::platform

‎src/modm/platform/dma/rp/module.lb

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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (c) 2022, Andrey Kunitsyn
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#
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# This file is part of the modm project.
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#
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# This Source Code Form is subject to the terms of the Mozilla Public
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# License, v. 2.0. If a copy of the MPL was not distributed with this
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# file, You can obtain one at http://mozilla.org/MPL/2.0/.
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# -----------------------------------------------------------------------------
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def init(module):
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module.name = ":platform:dma"
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module.description = "Direct Memory Access (DMA)"
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def prepare(module, options):
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module.depends(":cmsis:device", ":platform:clockgen")
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return options[":target"].has_driver("dma:rp20*")
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def build(env):
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env.substitutions = {"dma": env[":target"].get_driver("dma")}
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env.outbasepath = "modm/src/modm/platform/dma"
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env.template("dma.hpp.in")
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