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[stm32] Remove references to nonexistent 'a0' STM32H7 chip
1 parent 7a4df09 commit 9e7bdf4

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src/modm/platform/clock/stm32/module.lb

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ def build(env):
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((target["family"] == "f4") and target["name"] in ["46", "69", "79"])
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if target.family in ["h7"]:
89-
if target.name in ["a0", "a3", "b0", "b3"]:
89+
if target.name in ["a3", "b0", "b3"]:
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properties["cfgr_prescaler"] = "CDCFGR1"
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else:
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properties["cfgr_prescaler"] = "D1CFGR"
@@ -96,7 +96,7 @@ def build(env):
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properties["cfgr_prescaler"] = "CFGR"
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if target.family in ["h7"]:
99-
if target.name in ["a0", "a3", "b0", "b3"]:
99+
if target.name in ["a3", "b0", "b3"]:
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properties["cfgr2"] = "CDCFGR2"
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else:
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properties["cfgr2"] = "D2CFGR"
@@ -115,9 +115,9 @@ def build(env):
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else:
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properties["ccipr1"] = "CCIPR"
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118-
properties["d1"] = ("CD" if target.name in ["a0", "a3", "b0", "b3"] else "D1") \
118+
properties["d1"] = ("CD" if target.name in ["a3", "b0", "b3"] else "D1") \
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if target.family == "h7" else ""
120-
properties["d2"] = ("CD" if target.name in ["a0", "a3", "b0", "b3"] else "D2") \
120+
properties["d2"] = ("CD" if target.name in ["a3", "b0", "b3"] else "D2") \
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if target.family == "h7" else ""
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properties["cfgr3"] = ("SRDCFGR" if target.name in ["a0", "a3", "b0", "b3"] else "D3CFGR")
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properties["d3"] = ("SRD" if target.name in ["a0", "a3", "b0", "b3"] else "D3")

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