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[stm32] Add FDCAN support for H7 series
The H7 series supports a user-configured message RAM layout, rather than the static layout of past STM32 CAN IPs. The new message RAM is identical in structure and configurability to the ATSAM FDCAN IP. This commit merges the STM32 FDCAN and ATSAM FDCAN message RAM implementations. For H7 it also introduces lbuild parameters so the user can choose the amount of space available for each RX queue, each TX queue, and filters. This is independent for each FDCAN IP instance, although they share the same 10k RAM.
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‎README.md

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@@ -166,7 +166,7 @@ Please [discover modm's peripheral drivers for your specific device][discover].
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<td align="center">✅</td>
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<td align="center">✅</td>
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<td align="center">✅</td>
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<td align="center">○</td>
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<td align="center">✅</td>
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<td align="center">✕</td>
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<td align="center">✕</td>
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<td align="center">✅</td>

‎examples/nucleo_h723zg/can/main.cpp

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/*
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* Copyright (c) 2020, Raphael Lehmann
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*
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* This file is part of the modm project.
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/.
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*/
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#include <modm/board.hpp>
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#include <modm/debug/logger.hpp>
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#include <modm/board.hpp>
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using namespace modm::literals;
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// Set the log level
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#undef MODM_LOG_LEVEL
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#define MODM_LOG_LEVEL modm::log::INFO
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int
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main()
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{
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Board::initialize();
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MODM_LOG_INFO << "CAN Test Program" << modm::endl;
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MODM_LOG_INFO << "Initializing Fdcan1..." << modm::endl;
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// Initialize Fdcan1
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Fdcan1::connect<GpioA11::Rx, GpioA12::Tx>(Gpio::InputType::PullUp);
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Fdcan1::initialize<Board::SystemClock, 125_kbps, 1_pct, 500_kbps>(9);
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MODM_LOG_INFO << "Setting up Filter for Fdcan1..." << modm::endl;
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// Receive every extended id message
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Fdcan1::setExtendedFilter(0, Fdcan1::FilterConfig::Fifo0,
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modm::can::ExtendedIdentifier(0),
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modm::can::ExtendedMask(0));
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MODM_LOG_INFO << "Initializing Fdcan2..." << modm::endl;
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// Initialize Fdcan2
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Fdcan2::connect<GpioB5::Rx, GpioB6::Tx>(Gpio::InputType::PullUp);
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Fdcan2::initialize<Board::SystemClock, 125_kbps, 1_pct, 500_kbps>(12);
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MODM_LOG_INFO << "Setting up Filter for Fdcan2..." << modm::endl;
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// Receive every message
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Fdcan2::setExtendedFilter(0, Fdcan2::FilterConfig::Fifo0,
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modm::can::ExtendedIdentifier(0),
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modm::can::ExtendedMask(0));
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// Send a message
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MODM_LOG_INFO << "Sending message on Fdcan1..." << modm::endl;
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modm::can::Message msg1(1, 1);
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msg1.setExtended(true);
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msg1.data[0] = 0x11;
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Fdcan1::sendMessage(msg1);
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// Send a message
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MODM_LOG_INFO << "Sending message on Fdcan2..." << modm::endl;
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msg1.data[0] = 0x22;
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Fdcan2::sendMessage(msg1);
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while (true)
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{
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if (Fdcan1::isMessageAvailable())
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{
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MODM_LOG_INFO << "Fdcan1: Message is available..." << modm::endl;
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modm::can::Message message;
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Fdcan1::getMessage(message);
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MODM_LOG_INFO << message << modm::endl;
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}
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if (Fdcan2::isMessageAvailable())
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{
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MODM_LOG_INFO << "Fdcan2: Message is available..." << modm::endl;
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modm::can::Message message;
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Fdcan2::getMessage(message);
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MODM_LOG_INFO << message << modm::endl;
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}
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}
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return 0;
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}

‎examples/nucleo_h723zg/can/project.xml

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<library>
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<extends>modm:nucleo-h723zg</extends>
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<options>
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<option name="modm:build:build.path">../../../build/nucleo_h723zg/can</option>
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</options>
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<modules>
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<module>modm:debug</module>
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<module>modm:platform:can:1</module>
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<module>modm:platform:can:2</module>
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<module>modm:platform:can:3</module>
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<module>modm:build:scons</module>
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</modules>
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</library>

‎src/modm/board/nucleo_h723zg/board.hpp

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@@ -30,9 +30,12 @@ using namespace modm::literals;
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/// STM32H723ZG running at 550MHz from PLL clock generated from 8 MHz HSE
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struct SystemClock
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{
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static constexpr uint32_t Hse = 8_MHz;
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// Max 550MHz
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static constexpr uint32_t SysClk = 550_MHz;
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static constexpr uint32_t Pll1Q = SysClk / 4;
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static constexpr uint32_t Pll2Q = 120_MHz;
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// Max 550MHz
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static constexpr uint32_t Hclk = SysClk / 1; // D1CPRE
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static constexpr uint32_t Frequency = Hclk;
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static constexpr uint32_t LpUart1 = Apb4;
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static constexpr uint32_t Can1 = Apb1;
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static constexpr uint32_t Can2 = Apb1;
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static constexpr uint32_t Fdcan1 = Pll2Q;
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static constexpr uint32_t Fdcan2 = Pll2Q;
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static constexpr uint32_t Fdcan3 = Pll2Q;
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static constexpr uint32_t I2c1 = Apb1;
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static constexpr uint32_t I2c2 = Apb1;
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.pllR = 2, // 550 MHz / 2 = 275 MHz
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};
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Rcc::enablePll1(Rcc::PllSource::Hse, pllFactors1);
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// Use PLL2 for FDCAN 120MHz
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const Rcc::PllFactors pllFactors2{
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.range = Rcc::PllInputRange::MHz1_2,
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.pllM = 4, // 8MHz / M= 2MHz
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.pllN = 120, // 2MHz * N= 240MHz
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.pllP = 2, // 240MHz / P= 120MHz
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.pllQ = 2, // 240MHz / Q= 120MHz
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.pllR = 2, // 240MHz / R= 120MHz
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};
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Rcc::enablePll2(Rcc::PllSource::ExternalClock, pllFactors2);
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Rcc::setCanClockSource(Rcc::CanClockSource::Pll2Q);
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// Use PLL3 for USB 48MHz
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const Rcc::PllFactors pllFactors3{
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.range = Rcc::PllInputRange::MHz4_8,

‎src/modm/board/nucleo_h743zi/board.hpp

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@@ -29,8 +29,11 @@ using namespace modm::literals;
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/// STM32H743 running at 400MHz from the external 8MHz HSE
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struct SystemClock
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{
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static constexpr uint32_t Hse = 8_MHz;
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// NOTE: revision Y at 400MHz, only revision V runs at 480Mhz!!!
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static constexpr uint32_t SysClk = 400_MHz;
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static constexpr uint32_t Pll2Q = 120_MHz;
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// Max 400MHz or 480MHz
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static constexpr uint32_t Hclk = SysClk / 1; // D1CPRE
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static constexpr uint32_t Frequency = Hclk;
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static constexpr uint32_t LpUart1 = Apb4;
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static constexpr uint32_t Can1 = Apb1;
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static constexpr uint32_t Can2 = Apb1;
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static constexpr uint32_t Fdcan1 = Pll2Q;
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static constexpr uint32_t Fdcan2 = Pll2Q;
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static constexpr uint32_t I2c1 = Apb1;
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static constexpr uint32_t I2c2 = Apb1;
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.pllR = 10, // 400MHz / R= 40MHz
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};
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Rcc::enablePll1(Rcc::PllSource::ExternalClock, pllFactors1);
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// Use PLL2 for FDCAN 120MHz
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const Rcc::PllFactors pllFactors2{
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.range = Rcc::PllInputRange::MHz1_2,
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.pllM = 4, // 8MHz / M= 2MHz
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.pllN = 120, // 2MHz * N= 240MHz
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.pllP = 2, // 240MHz / P= 120MHz
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.pllQ = 2, // 240MHz / Q= 120MHz
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.pllR = 2, // 240MHz / R= 120MHz
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};
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Rcc::enablePll2(Rcc::PllSource::ExternalClock, pllFactors2);
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Rcc::setCanClockSource(Rcc::CanClockSource::Pll2Q);
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// Use PLL3 for USB 48MHz
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const Rcc::PllFactors pllFactors3{
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.range = Rcc::PllInputRange::MHz4_8,

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