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salkiniumrleh
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Move stack into the fastest DMA-able memory
1 parent 38ddee9 commit e07f57d

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4 files changed

+21
-12
lines changed

4 files changed

+21
-12
lines changed

src/modm/platform/core/cortex/ram.ld.in

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88

99
%% if vector_table_location == "ram"
1010
/* Round up the number of vector table entries to the nearest power-of-two and multiply by 8. */
11-
__vec_alignment = (1 << LOG2CEIL({{ number_of_interrupts + 16 }})) * 8;
11+
__vec_alignment = (1 << LOG2CEIL({{ highest_irq + 16 }})) * 8;
1212
/* compute the vector table offset from start of RAM */
1313
__vec_offset = ALIGN(TOTAL_STACK_SIZE, __vec_alignment);
1414
%% else

src/modm/platform/core/stm32/dccm.ld.in

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,14 @@
66
%% set table_copy = []
77
%% set table_zero = []
88

9+
%% if vector_table_location == "ram"
10+
/* Round up the number of vector table entries to the nearest power-of-two and multiply by 8. */
11+
__vec_alignment = (1 << LOG2CEIL({{ highest_irq + 16 }})) * 8;
12+
/* compute the vector table offset from start of RAM */
13+
__vec_offset = ALIGN(TOTAL_STACK_SIZE, __vec_alignment);
14+
%% else
15+
__vec_offset = TOTAL_STACK_SIZE;
16+
%% endif
917

1018
SECTIONS
1119
{
@@ -16,6 +24,8 @@ SECTIONS
1624
{{ linker.section_rom("FLASH") }}
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1826

27+
{{ linker.section_stack(cont_ram_regions[0].name|upper, "__vec_offset - TOTAL_STACK_SIZE") }}
28+
1929
%% if vector_table_location == "ram"
2030
{{ linker.section_vector_ram(cont_ram_regions[0].name|upper) }}
2131
%% endif
@@ -37,9 +47,6 @@ SECTIONS
3747
%% endif
3848

3949

40-
{{ linker.section_stack("CCM") }}
41-
42-
/* CCM can only be accessed by D-Bus, do not place .fastcode here! */
4350
{{ linker.section("CCM AT >FLASH", "fastdata", sections=["data_ccm"]) }}
4451
%% do table_copy.append("fastdata")
4552

src/modm/platform/core/stm32/module.lb

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ def build(env):
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7171
def post_build(env):
7272
env.substitutions = env.query("::cortex-m:linkerscript")
73+
env.substitutions.update(env.query("::cortex-m:vector_table"))
7374
env.outbasepath = "modm/link"
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7576
linkerscript = "../cortex/ram.ld.in"

src/modm/platform/core/stm32/module.md

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,7 @@ SRAMs explicitly to free up the space in the lower sections.
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Some STM32F4 have a battery-backed backup SRAM and a single-cycle CCM that is
107107
only accessible to the core via the D-Code bus, thus the CCM is not DMA-able.
108+
Therefore the main stack is placed into SRAM, even though it is slower than CCM.
108109
109110
```
110111
┌────────────────────────┐◄ __backup_end
@@ -133,17 +134,17 @@ only accessible to the core via the D-Code bus, thus the CCM is not DMA-able.
133134
│ .data_sram1 │
134135
│ .data │
135136
│ .fastcode │
136-
SRAM1 │ (.vector_ram) │◄ only if remapped into RAM
137+
│ (.vector_ram) │◄ only if remapped into RAM
138+
│ +PROCESS_STACK_SIZE │◄ __process_stack_top
139+
SRAM1 │ +MAIN_STACK_SIZE │◄ __main_stack_top
137140
0x2000 0000 └────────────────────────┘◄ __sram1_start
138141

139142
┌────────────────────────┐◄ __ccm_end
140-
│ +HEAP_CCM │
141-
D-Code │ .noinit_ccm │
142-
only │ .bss_ccm │
143-
access │ .data_ccm │
144-
│ .fastdata │
145-
│ +PROCESS_STACK_SIZE │◄ __process_stack_top
146-
CCM │ +MAIN_STACK_SIZE │◄ __main_stack_top
143+
D-Code │ +HEAP_CCM │
144+
only │ .noinit_ccm │
145+
access │ .bss_ccm │
146+
│ .data_ccm │
147+
CCM │ .fastdata │
147148
0x1000 0000 └────────────────────────┘◄ __ccm_start
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149150
┌────────────────────────┐◄ __flash_end

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