Skip to content

Commit e1c3de1

Browse files
salkiniumsalkinium
committed
[rcc] Move STM32F3 RCC to new API
1 parent 2bcff2c commit e1c3de1

File tree

6 files changed

+587
-81
lines changed

6 files changed

+587
-81
lines changed

‎src/modm/board/disco_f303vc/board.hpp‎

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,11 @@ using namespace modm::literals;
3636
struct SystemClock
3737
{
3838
static constexpr uint32_t Hse = 8_MHz;
39-
static constexpr uint32_t Frequency = 72_MHz;
39+
static constexpr Rcc::PllConfig pll{.Prediv = 1, .Mul = 9};
40+
static constexpr uint32_t Pll = Hse / pll.Prediv * pll.Mul;
41+
static_assert(Pll == Rcc::MaxFrequency);
42+
43+
static constexpr uint32_t Frequency = Pll;
4044
static constexpr uint32_t Ahb = Frequency;
4145
static constexpr uint32_t Apb1 = Frequency / 2;
4246
static constexpr uint32_t Apb2 = Frequency;
@@ -95,26 +99,20 @@ struct SystemClock
9599
static bool inline
96100
enable()
97101
{
98-
Rcc::enableRealTimeClock(Rcc::RealTimeClockSource::ExternalClock);
99-
100-
Rcc::enableExternalClock(); // 8MHz
101-
const Rcc::PllFactors pllFactors{
102-
.pllMul = 9,
103-
.pllPrediv = 1,
104-
.usbPrediv = Rcc::UsbPrescaler::Div1_5
105-
};
106-
Rcc::enablePll(Rcc::PllSource::ExternalClock, pllFactors);
107-
// set flash latency for 72MHz
102+
Rcc::enableHseClock();
103+
108104
Rcc::setFlashLatency<Frequency>();
109-
// switch system clock to PLL output
110-
Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
111-
Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1);
112-
// APB1 has max. 36MHz
113-
Rcc::setApb1Prescaler(Rcc::Apb1Prescaler::Div2);
114-
Rcc::setApb2Prescaler(Rcc::Apb2Prescaler::Div1);
115-
// update frequencies for busy-wait delay functions
116105
Rcc::updateCoreFrequency<Frequency>();
117106

107+
Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1);
108+
Rcc::setApb1Prescaler(Rcc::ApbPrescaler::Div2);
109+
Rcc::setApb2Prescaler(Rcc::ApbPrescaler::Div1);
110+
Rcc::setUsbClockPrescaler(Rcc::UsbPrescaler::Div1_5);
111+
112+
Rcc::enablePll(Rcc::PllSource::HsePrediv, pll);
113+
Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
114+
Rcc::setRealTimeClockSource(Rcc::RealTimeClockSource::HseDiv32);
115+
118116
return true;
119117
}
120118
};

‎src/modm/board/nucleo_f303k8/board.hpp‎

Lines changed: 17 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -27,10 +27,13 @@ namespace Board
2727
using namespace modm::literals;
2828

2929
/// STM32F303K8 running at 64MHz generated from the internal 8MHz clock
30-
// Dummy clock for devices
3130
struct SystemClock
3231
{
33-
static constexpr uint32_t Frequency = 64_MHz;
32+
static constexpr Rcc::PllConfig pll{.Mul = 16};
33+
static constexpr uint32_t Pll = Rcc::HsiFrequency / 2 * pll.Mul;
34+
static_assert(Pll <= Rcc::MaxFrequency);
35+
36+
static constexpr uint32_t Frequency = Pll;
3437
static constexpr uint32_t Ahb = Frequency;
3538
static constexpr uint32_t Apb1 = Frequency / 2;
3639
static constexpr uint32_t Apb2 = Frequency;
@@ -48,7 +51,7 @@ struct SystemClock
4851
static constexpr uint32_t Usart3 = Apb1;
4952

5053
// I2C1 clock source is HSI per default
51-
static constexpr uint32_t I2c1 = 8_MHz;
54+
static constexpr uint32_t I2c1 = Rcc::HsiFrequency;
5255

5356
static constexpr uint32_t Apb1Timer = Apb1 * 2;
5457
static constexpr uint32_t Apb2Timer = Apb2 * 1;
@@ -66,27 +69,20 @@ struct SystemClock
6669
static bool inline
6770
enable()
6871
{
69-
Rcc::enableLowSpeedInternalClock();
70-
Rcc::enableRealTimeClock(Rcc::RealTimeClockSource::Lsi);
71-
72-
Rcc::enableInternalClock(); // 8MHz
73-
// 8MHz / 2 * 16 = 64MHz
74-
const Rcc::PllFactors pllFactors{
75-
.pllMul = 16,
76-
.pllPrediv = 2, // only used with Hse
77-
};
78-
Rcc::enablePll(Rcc::PllSource::HsiDiv2, pllFactors);
79-
// set flash latency for 64MHz
72+
Rcc::enableLsiClock();
73+
Rcc::enableHsiClock();
74+
8075
Rcc::setFlashLatency<Frequency>();
81-
// switch system clock to PLL output
82-
Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
83-
Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1);
84-
// APB1 has max. 36MHz
85-
Rcc::setApb1Prescaler(Rcc::Apb1Prescaler::Div2);
86-
Rcc::setApb2Prescaler(Rcc::Apb2Prescaler::Div1);
87-
// update frequencies for busy-wait delay functions
8876
Rcc::updateCoreFrequency<Frequency>();
8977

78+
Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1);
79+
Rcc::setApb1Prescaler(Rcc::ApbPrescaler::Div2);
80+
Rcc::setApb2Prescaler(Rcc::ApbPrescaler::Div1);
81+
82+
Rcc::enablePll(Rcc::PllSource::HsiDiv2, pll);
83+
Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
84+
Rcc::setRealTimeClockSource(Rcc::RealTimeClockSource::Lsi);
85+
9086
return true;
9187
}
9288
};

‎src/modm/board/nucleo_f303re/board.hpp‎

Lines changed: 20 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,11 @@ using namespace modm::literals;
3030
/// STM32F303RE running at 64MHz generated from the internal 8MHz clock
3131
struct SystemClock
3232
{
33-
static constexpr uint32_t Frequency = 64_MHz;
33+
static constexpr Rcc::PllConfig pll{.Mul = 16};
34+
static constexpr uint32_t Pll = Rcc::HsiFrequency / 2 * pll.Mul;
35+
static_assert(Pll <= Rcc::MaxFrequency);
36+
37+
static constexpr uint32_t Frequency = Pll;
3438
static constexpr uint32_t Ahb = Frequency;
3539
static constexpr uint32_t Apb1 = Frequency / 2;
3640
static constexpr uint32_t Apb2 = Frequency;
@@ -48,9 +52,9 @@ struct SystemClock
4852
static constexpr uint32_t Usart3 = Apb1;
4953

5054
// I2C clock source is HSI by default
51-
static constexpr uint32_t I2c1 = 8_MHz;
52-
static constexpr uint32_t I2c2 = 8_MHz;
53-
static constexpr uint32_t I2c3 = 8_MHz;
55+
static constexpr uint32_t I2c1 = Rcc::HsiFrequency;
56+
static constexpr uint32_t I2c2 = Rcc::HsiFrequency;
57+
static constexpr uint32_t I2c3 = Rcc::HsiFrequency;
5458

5559
static constexpr uint32_t Apb1Timer = Apb1 * 2;
5660
static constexpr uint32_t Apb2Timer = Apb2 * 1;
@@ -68,27 +72,21 @@ struct SystemClock
6872
static bool inline
6973
enable()
7074
{
71-
Rcc::enableLowSpeedExternalCrystal();
72-
Rcc::enableRealTimeClock(Rcc::RealTimeClockSource::LowSpeedExternalCrystal);
73-
74-
Rcc::enableInternalClock(); // 8MHz
75-
// 8MHz / 2 * 16 = 64MHz
76-
const Rcc::PllFactors pllFactors{
77-
.pllMul = 16,
78-
.pllPrediv = 2,
79-
};
80-
Rcc::enablePll(Rcc::PllSource::InternalClock, pllFactors);
81-
// set flash latency for 64MHz
75+
Rcc::enableLseCrystal();
76+
Rcc::enableHsiClock();
77+
8278
Rcc::setFlashLatency<Frequency>();
83-
// switch system clock to PLL output
84-
Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
85-
Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1);
86-
// APB1 has max. 36MHz
87-
Rcc::setApb1Prescaler(Rcc::Apb1Prescaler::Div2);
88-
Rcc::setApb2Prescaler(Rcc::Apb2Prescaler::Div1);
89-
// update frequencies for busy-wait delay functions
9079
Rcc::updateCoreFrequency<Frequency>();
9180

81+
Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1);
82+
Rcc::setApb1Prescaler(Rcc::ApbPrescaler::Div2);
83+
Rcc::setApb2Prescaler(Rcc::ApbPrescaler::Div1);
84+
85+
Rcc::enablePll(Rcc::PllSource::HsiDiv2, pll);
86+
Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
87+
Rcc::setRealTimeClockSource(Rcc::RealTimeClockSource::Lse);
88+
89+
9290
return true;
9391
}
9492
};

‎src/modm/board/nucleo_f334r8/board.hpp‎

Lines changed: 16 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,11 @@ using namespace modm::literals;
2929
/// STM32F334R8 running at 64MHz generated from the internal 8MHz clock
3030
struct SystemClock
3131
{
32-
static constexpr uint32_t Frequency = 64_MHz;
32+
static constexpr Rcc::PllConfig pll{.Mul = 16};
33+
static constexpr uint32_t Pll = Rcc::HsiFrequency / 2 * pll.Mul;
34+
static_assert(Pll <= Rcc::MaxFrequency);
35+
36+
static constexpr uint32_t Frequency = Pll;
3337
static constexpr uint32_t Ahb = Frequency;
3438
static constexpr uint32_t Apb1 = Frequency / 2;
3539
static constexpr uint32_t Apb2 = Frequency;
@@ -65,27 +69,20 @@ struct SystemClock
6569
static bool inline
6670
enable()
6771
{
68-
Rcc::enableLowSpeedExternalCrystal();
69-
Rcc::enableRealTimeClock(Rcc::RealTimeClockSource::LowSpeedExternalCrystal);
70-
71-
Rcc::enableInternalClock(); // 8MHz
72-
// 8MHz / 2 * 16 = 64MHz
73-
const Rcc::PllFactors pllFactors{
74-
.pllMul = 16,
75-
.pllPrediv = 2, // fixed (/2) for Hsi
76-
};
77-
Rcc::enablePll(Rcc::PllSource::HsiDiv2, pllFactors);
78-
// set flash latency for 64MHz
72+
Rcc::enableLseCrystal();
73+
Rcc::enableHsiClock();
74+
7975
Rcc::setFlashLatency<Frequency>();
80-
// switch system clock to PLL output
81-
Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
82-
Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1);
83-
// APB1 has max. 36MHz
84-
Rcc::setApb1Prescaler(Rcc::Apb1Prescaler::Div2);
85-
Rcc::setApb2Prescaler(Rcc::Apb2Prescaler::Div1);
86-
// update frequencies for busy-wait delay functions
8776
Rcc::updateCoreFrequency<Frequency>();
8877

78+
Rcc::setAhbPrescaler(Rcc::AhbPrescaler::Div1);
79+
Rcc::setApb1Prescaler(Rcc::ApbPrescaler::Div2);
80+
Rcc::setApb2Prescaler(Rcc::ApbPrescaler::Div1);
81+
82+
Rcc::enablePll(Rcc::PllSource::HsiDiv2, pll);
83+
Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
84+
Rcc::setRealTimeClockSource(Rcc::RealTimeClockSource::Lse);
85+
8986
return true;
9087
}
9188
};

‎src/modm/platform/clock/stm32/module.lb‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -146,13 +146,14 @@ def build(env):
146146
ids += device.get_driver(driver)["instance"]
147147
return list(map(int, ids))
148148

149-
if t.family in ["h5", "u0", "g0", "u3", "c0", "f0", "l0", "f1", "f2"]:
149+
if t.family in ["h5", "u0", "g0", "u3", "c0", "f0", "l0", "f1", "f2", "f3"]:
150150
p["uart_ids"] = instances("usart", "uart")
151151
p["lpuart_ids"] = instances("lpuart")
152152
p["spi_ids"] = instances("spi")
153153
p["i2c_ids"] = instances("i2c")
154154
p["tim_ids"] = instances("tim")
155155
p["lptim_ids"] = instances("lptim")
156+
p["adc_ids"] = instances("adc")
156157
env.template(f"rcc_{t.family}.hpp.in", "rcc.hpp")
157158
else:
158159
env.template("rcc.hpp.in")

0 commit comments

Comments
 (0)