[rp] Add clocks module

Author: andryblack

src/modm/platform/clock/rp/clocks.cpp

@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2022, Andrey Kunitsyn
+ *
+ * This file is part of the modm project.
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/.
+ */
+// ----------------------------------------------------------------------------
+
+#include "clocks.hpp"
+
+#include <hardware/structs/xosc.h>
+
+#include "../device.hpp"
+
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 1
+#endif
+
+// CMSIS Core compliance
+constinit uint32_t modm_fastdata SystemCoreClock(modm::platform::ClockControl::BootFrequency);
+
+namespace modm::platform
+{
+constinit uint16_t modm_fastdata delay_fcpu_MHz(computeDelayMhz(ClockControl::BootFrequency));
+constinit uint16_t modm_fastdata delay_ns_per_loop(computeDelayNsPerLoop(ClockControl::BootFrequency));
+
+static uint32_t configured_freq[CLK_COUNT];
+
+void
+ClockControl::enableExternalCrystal(uint32_t freq)
+{
+	// Assumes 1-15 MHz input, checked above.
+	xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ;
+
+	uint32_t delay = ((((freq / 1000) + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER);
+
+	// Set xosc startup delay
+	xosc_hw->startup = delay;
+
+	// Set the enable bit now that we have set freq range and startup delay
+	hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB);
+
+	// Wait for XOSC to be stable
+	while (!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)) __NOP();
+}
+
+void
+ClockControl::configureImpl(Clock clk, uint32_t src, uint32_t auxsrc, uint32_t div, uint32_t freq)
+{
+	clock_hw_t *clock = &clocks_hw->clk[uint32_t(clk)];
+	// If increasing divisor, set divisor before source. Otherwise set source
+	// before divisor. This avoids a momentary overspeed when e.g. switching
+	// to a faster source and increasing divisor to compensate.
+	if (div > clock->div) clock->div = div;
+	// If switching a glitchless slice to an aux source, switch
+	// away from aux *first* to avoid passing glitches when changing aux mux.
+	// Assume (!!!) glitchless source 0 is no faster than the aux source.
+	if (src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX)
+	{
+		hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
+		while (!(clock->selected & 1u)) __NOP();
+	}
+	// If no glitchless mux, cleanly stop the clock to avoid glitches
+	// propagating when changing aux mux. Note it would be a really bad idea
+	// to do this on one of the glitchless clocks.
+	else
+	{
+		// Disable clock. On clk_ref and clk_sys this does nothing,
+		// all other clocks have the ENABLE bit in the same position.
+		hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
+		if (configured_freq[uint32_t(clk)] > 0)
+		{
+			// Delay for 3 cycles of the target clock, for ENABLE propagation.
+			// Note XOSC_COUNT is not helpful here because XOSC is not
+			// necessarily running, nor is timer... so, 3 cycles per loop:
+			uint32_t delay_cyc = configured_freq[clk_sys] / configured_freq[uint32_t(clk)] + 1;
+			asm volatile(
+				".syntax unified \n\t"
+				"1: \n\t"
+				"subs %0, #1 \n\t"
+				"bne 1b"
+				: "+r"(delay_cyc));
+		}
+	}
+
+	// Set aux mux first, and then glitchless mux
+	hw_write_masked(&clock->ctrl, (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB),
+					CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS);
+
+	hw_write_masked(&clock->ctrl, src << CLOCKS_CLK_REF_CTRL_SRC_LSB,
+						CLOCKS_CLK_REF_CTRL_SRC_BITS);
+	while (!(clock->selected & (1u << src))) __NOP();
+
+	// Enable clock. On clk_ref and clk_sys this does nothing,
+	// all other clocks have the ENABLE bit in the same position.
+	hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
+
+	// Now that the source is configured, we can trust that the user-supplied
+	// divisor is a safe value.
+	clock->div = div;
+	// Store the configured frequency
+	configured_freq[uint32_t(clk)] = freq;
+}
+
+void
+ClockControl::configureImpl(Clock clk, uint32_t auxsrc, uint32_t div, uint32_t freq)
+{
+
+	clock_hw_t *clock = &clocks_hw->clk[uint32_t(clk)];
+	// If increasing divisor, set divisor before source. Otherwise set source
+	// before divisor. This avoids a momentary overspeed when e.g. switching
+	// to a faster source and increasing divisor to compensate.
+	if (div > clock->div) clock->div = div;
+	// Disable clock. On clk_ref and clk_sys this does nothing,
+	// all other clocks have the ENABLE bit in the same position.
+	hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
+	if (configured_freq[uint32_t(clk)] > 0)
+	{
+		// Delay for 3 cycles of the target clock, for ENABLE propagation.
+		// Note XOSC_COUNT is not helpful here because XOSC is not
+		// necessarily running, nor is timer... so, 3 cycles per loop:
+		uint32_t delay_cyc = configured_freq[clk_sys] / configured_freq[uint32_t(clk)] + 1;
+		asm volatile(
+			".syntax unified \n\t"
+			"1: \n\t"
+			"subs %0, #1 \n\t"
+			"bne 1b"
+			: "+r"(delay_cyc));
+	}
+
+	// Set aux mux
+	hw_write_masked(&clock->ctrl, (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB),
+					CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS);
+
+	// Enable clock. On clk_ref and clk_sys this does nothing,
+	// all other clocks have the ENABLE bit in the same position.
+	hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
+
+	// Now that the source is configured, we can trust that the user-supplied
+	// divisor is a safe value.
+	clock->div = div;
+	// Store the configured frequency
+	configured_freq[uint32_t(clk)] = freq;
+}
+}  // namespace modm::platform

src/modm/platform/clock/rp/clocks.hpp.in

@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2022, Andrey Kunitsyn
+ *
+ * This file is part of the modm project.
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/.
+ */
+// ----------------------------------------------------------------------------
+
+#pragma once
+
+#include <hardware/structs/clocks.h>
+#include <hardware/structs/pll.h>
+#include <stdint.h>
+
+#include <modm/architecture/interface/delay.hpp>
+#include <modm/platform/core/resets.hpp>
+#include <modm/platform/device.hpp>
+
+namespace modm::platform
+{
+
+/// @ingroup modm_platform_clockgen
+class ClockControl
+{
+public:
+	enum class Clock
+	{
+%% for clk in clocks
+		{{ clk['name'] | capitalize }} = {{ clk['idx'] | int }},
+%% endfor
+	};
+	enum class ClockSrc
+	{
+%% for src in sources
+		{{ src }},
+%% endfor
+	};
+
+	enum class Pll
+	{
+		Sys,
+		Usb,
+	};
+
+	static constexpr uint32_t BootFrequency = 125'000'000;  // after bootloader
+
+protected:
+	/// @cond
+	struct InvalidConfig
+	{
+		static constexpr uint32_t src = 0xffffffff;
+		static constexpr uint32_t aux_src = 0xffffffff;
+	};
+
+	template<Clock clk, ClockSrc src>
+	struct SrcConfig : InvalidConfig
+	{};
+
+	static void
+	configureImpl(Clock clk, uint32_t src, uint32_t auxsrc, uint32_t div, uint32_t freq);
+	static void
+	configureImpl(Clock clk, uint32_t auxsrc, uint32_t div, uint32_t freq);
+
+	static constexpr bool
+	isGlitchless(Clock clk)
+	{
+%% for clk in clocks if clk['glitchless'] == "true"
+		if (clk == Clock::{{ clk['name'] | capitalize }}) return true;
+%% endfor
+		return false;
+	}
+	/// @endcond
+
+public:
+	static inline void
+	disableResus()
+	{
+		clocks_hw->resus.ctrl = 0;
+	}
+
+	static void
+	enableExternalCrystal(uint32_t freq);
+
+	template<Clock clk>
+	static void
+	disableAux()
+	{
+		static_assert(isGlitchless(clk),"This clock has only aux sources");
+%% for clk in clocks if clk['glitchless'] == "true"
+		{% if not loop.first %}else {% endif %}if constexpr (clk == Clock::{{ clk['name'] | capitalize }})
+		{
+			hw_clear_bits(&clocks_hw->clk[uint32_t(clk)].ctrl, CLOCKS_CLK_{{ clk['name'] | upper }}_CTRL_SRC_BITS);
+		}
+%% endfor
+		while (clocks_hw->clk[uint32_t(clk)].selected != 0x1) __NOP();
+	}
+
+	template<Pll pll_name, uint32_t refdiv, uint32_t pll_mul, uint32_t post_div1,
+			 uint32_t post_div2>
+	static void
+	initPll()
+	{
+		pll_hw_t* pll = pll_name == Pll::Sys ? pll_sys_hw : pll_usb_hw;
+		static_assert(pll_mul >= 16 and pll_mul <= 320, "invalid pll_mul");
+		// Check divider ranges
+		static_assert((post_div1 >= 1 and post_div1 <= 7) and (post_div2 >= 1 and post_div2 <= 7),
+					  "invalid post div");
+		// post_div1 should be >= post_div2
+		// from appnote page 11
+		// postdiv1 is designed to operate with a higher input frequency
+		// than postdiv2
+		static_assert(post_div2 <= post_div1, "post_div2 vs post_div1");
+		uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) | (post_div2 << PLL_PRIM_POSTDIV2_LSB);
+		if ((pll->cs & PLL_CS_LOCK_BITS) and (refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) and
+			(pll_mul == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) and
+			(pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS & PLL_PRIM_POSTDIV2_BITS))))
+		{
+			// do not disrupt PLL that is already correctly configured and operating
+			return;
+		}
+		uint32_t pll_reset = (Pll::Usb == pll_name) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS;
+		Resets::reset(pll_reset);
+		Resets::unresetWait(pll_reset);
+
+		// Load VCO-related dividers before starting VCO
+		pll->cs = refdiv;
+		pll->fbdiv_int = pll_mul;
+
+		// Turn on PLL
+		uint32_t power = PLL_PWR_PD_BITS |    // Main power
+						 PLL_PWR_VCOPD_BITS;  // VCO Power
+
+		hw_clear_bits(&pll->pwr, power);
+
+		// Wait for PLL to lock
+		while (!(pll->cs & PLL_CS_LOCK_BITS)) __NOP();
+
+		// Set up post dividers
+		pll->prim = pdiv;
+
+		// Turn on post divider
+		hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS);
+	}
+
+	/**
+	 * Valid connections are:
+%% for clk in clocks
+%% for src in clk.source
+	 * - Clock::{{ clk.name | capitalize }} -> ClockSrc::{{ src.cname }}
+%% endfor
+%% endfor
+	 */
+	template<Clock clk, ClockSrc src, uint32_t SrcFreq, uint32_t TargetFreq>
+	static void
+	configureClock()
+	{
+		using Config = SrcConfig<clk, src>;
+		constexpr uint32_t div = (uint64_t(SrcFreq) << 8) / TargetFreq;
+		static_assert(((uint64_t(SrcFreq) << 8) / div) == TargetFreq, "invalid freq");
+
+		if constexpr (isGlitchless(clk))
+		{
+			static_assert(Config::src != InvalidConfig::src and
+				Config::aux_src != InvalidConfig::aux_src,
+				"Invalid clock config");
+			configureImpl(clk, Config::src, Config::aux_src, div, TargetFreq);
+		}
+		else {
+			static_assert(Config::aux_src != InvalidConfig::aux_src, "Invalid clock config");
+			configureImpl(clk, Config::aux_src, div, TargetFreq);
+		}
+	}
+
+	template<uint32_t Core_Hz>
+	static void
+	updateCoreFrequency()
+	{
+		SystemCoreClock = Core_Hz;
+		delay_fcpu_MHz = computeDelayMhz(Core_Hz);
+		delay_ns_per_loop = computeDelayNsPerLoop(Core_Hz);
+	}
+};
+
+/// @cond
+// clocks connections matrix
+%% for clk in clocks
+// {{ clk.name | capitalize }}
+%% for src in clk.source
+template<>
+struct ClockControl::SrcConfig<ClockControl::Clock::{{ clk.name | capitalize }}, ClockControl::ClockSrc::{{ src.cname }}>
+{
+%% if clk.glitchless == 'true'
+	static constexpr uint32_t src = {{ src.src | int }};
+%% endif
+	static constexpr uint32_t aux_src = {{ src.aux | int }};
+};
+%% endfor
+%% endfor
+/// @endcond
+
+}  // namespace modm::platform