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| 1 | +#pragma once |
| 2 | + |
| 3 | +#include "./Arduino_GFX.h" |
| 4 | +#include "../Arduino_TFT.h" |
| 5 | + |
| 6 | +#define GC9C01_TFTWIDTH 360 |
| 7 | +#define GC9C01_TFTHEIGHT 360 |
| 8 | + |
| 9 | +#define GC9C01_RST_DELAY 200 ///< delay ms wait for reset finish |
| 10 | +#define GC9C01_SLPIN_DELAY 120 ///< delay ms wait for sleep in finish |
| 11 | +#define GC9C01_SLPOUT_DELAY 120 ///< delay ms wait for sleep out finish |
| 12 | + |
| 13 | +#define GC9C01_NOP 0x00 |
| 14 | +#define GC9C01_SWRESET 0x01 |
| 15 | +#define GC9C01_RDDID 0x04 |
| 16 | +#define GC9C01_RDDST 0x09 |
| 17 | + |
| 18 | +#define GC9C01_SLPIN 0x10 |
| 19 | +#define GC9C01_SLPOUT 0x11 |
| 20 | +#define GC9C01_PTLON 0x12 |
| 21 | +#define GC9C01_NORON 0x13 |
| 22 | + |
| 23 | +#define GC9C01_INVOFF 0x20 |
| 24 | +#define GC9C01_INVON 0x21 |
| 25 | +#define GC9C01_DISPOFF 0x28 |
| 26 | +#define GC9C01_DISPON 0x29 |
| 27 | + |
| 28 | +#define GC9C01_CASET 0x2A |
| 29 | +#define GC9C01_RASET 0x2B |
| 30 | +#define GC9C01_RAMWR 0x2C |
| 31 | +#define GC9C01_RAMRD 0x2E |
| 32 | + |
| 33 | +#define GC9C01_PTLAR 0x30 |
| 34 | +#define GC9C01_COLMOD 0x3A |
| 35 | +#define GC9C01_MADCTL 0x36 |
| 36 | + |
| 37 | +#define GC9C01_MADCTL_MY 0x80 |
| 38 | +#define GC9C01_MADCTL_MX 0x40 |
| 39 | +#define GC9C01_MADCTL_MV 0x20 |
| 40 | +#define GC9C01_MADCTL_ML 0x10 |
| 41 | +#define GC9C01_MADCTL_RGB 0x00 |
| 42 | + |
| 43 | +#define GC9C01_RDID1 0xDA |
| 44 | +#define GC9C01_RDID2 0xDB |
| 45 | +#define GC9C01_RDID3 0xDC |
| 46 | +#define GC9C01_RDID4 0xDD |
| 47 | + |
| 48 | +static const uint8_t gc9c01_init_operations[] = { |
| 49 | + BEGIN_WRITE, |
| 50 | + WRITE_COMMAND_8, 0xfe, // internal reg enable |
| 51 | + WRITE_COMMAND_8, 0xef, // internal reg enable |
| 52 | + WRITE_C8_D8, 0x80, 0x11, // reg_en for 70\74 |
| 53 | + WRITE_C8_D8, 0x81, 0x70, // reg_en for 7C\7D\7E |
| 54 | + WRITE_C8_D8, 0x82, 0x09, // reg_en for 90\93 |
| 55 | + WRITE_C8_D8, 0x83, 0x03, // reg_en for 98\99 |
| 56 | + WRITE_C8_D8, 0x84, 0x20, // reg_en for B5 |
| 57 | + WRITE_C8_D8, 0x85, 0x42, // reg_en for B9\BE |
| 58 | + WRITE_C8_D8, 0x86, 0xfc, // reg_en for C2~7 |
| 59 | + WRITE_C8_D8, 0x87, 0x09, // reg_en for C8\CB |
| 60 | + WRITE_C8_D8, 0x89, 0x10, // reg_en for EC |
| 61 | + WRITE_C8_D8, 0x8A, 0x4f, // reg_en for F0~3\F6 |
| 62 | + WRITE_C8_D8, 0x8C, 0x59, // reg_en for 60\63\64\66 |
| 63 | + WRITE_C8_D8, 0x8D, 0x51, // reg_en for 68\6C\6E |
| 64 | + WRITE_C8_D8, 0x8E, 0xae, // reg_en for A1~3\A5\A7 |
| 65 | + WRITE_C8_D8, 0x8F, 0xf3, // reg_en for AC~F\A8\A9 |
| 66 | + WRITE_C8_D8, 0x36, 0x00, |
| 67 | + WRITE_C8_D8, 0x3a, 0x05, // 565 frame |
| 68 | + WRITE_C8_D8, 0xEC, 0x77, |
| 69 | + |
| 70 | + WRITE_C8_BYTES, 0x74, 6, // rtn 60Hz |
| 71 | + 0x01, 0x80, 0x00, 0x00, |
| 72 | + 0x00, 0x00, |
| 73 | + |
| 74 | + WRITE_C8_D8, 0x98, 0x3E, |
| 75 | + WRITE_C8_D8, 0x99, 0x3E, |
| 76 | + WRITE_C8_D8, 0xC3, 0x2A, |
| 77 | + WRITE_C8_D8, 0xC4, 0x18, |
| 78 | + WRITE_C8_D16, 0xA1, 0x01, 0x04, // SRAM RD OPTION |
| 79 | + WRITE_C8_D16, 0xA2, 0x01, 0x04, // SRAM RD OPTION |
| 80 | + WRITE_C8_D8, 0xA9, 0x1C, // IREF=9.8uA |
| 81 | + WRITE_C8_D16, 0xA5, 0x11, 0x09, // VDDML=1.24V |
| 82 | + WRITE_C8_D8, 0xB9, 0x8A, // RTERM=101O |
| 83 | + WRITE_C8_D8, 0xA8, 0x5E, // VBG_BUF=1.003V, DVDD=1.543V |
| 84 | + WRITE_C8_D8, 0xA7, 0x40, // BIAS=10.2uA |
| 85 | + WRITE_C8_D8, 0xAF, 0x73, // VDDSOU=1.715V ,VDDGM=2.002V |
| 86 | + WRITE_C8_D8, 0xAE, 0x44, // VREE=2.475V,VRDD=2.335V |
| 87 | + WRITE_C8_D8, 0xAD, 0x38, // VRGL=1.635V ,VDDSF=2.018V |
| 88 | + WRITE_C8_D8, 0xA3, 0x5D, // OSC=53.7MHz |
| 89 | + WRITE_C8_D8, 0xC2, 0x02, // VREG_VREF=2.805V |
| 90 | + WRITE_C8_D8, 0xC5, 0x11, // VREG1A=5.99V |
| 91 | + WRITE_C8_D8, 0xC6, 0x0E, // VREG1B=1.505V |
| 92 | + WRITE_C8_D8, 0xC7, 0x13, // VREG2A=-2.995V |
| 93 | + WRITE_C8_D8, 0xC8, 0x0D, // VREG2B=1.497V |
| 94 | + WRITE_C8_D8, 0xCB, 0x02, // 6.09V |
| 95 | + WRITE_C8_D16, 0x7C, 0xB6, 0x26, // 13.12V |
| 96 | + WRITE_C8_D8, 0xAC, 0x24, // VGLO=-8.35V |
| 97 | + WRITE_C8_D8, 0xF6, 0x80, // EPF=2 |
| 98 | + WRITE_C8_D16, 0xB5, 0x09, 0x09, // VBP |
| 99 | + |
| 100 | + WRITE_C8_BYTES, 0x60, 4, // STV1&2 |
| 101 | + 0x38, 0x0B, 0x5B, 0x56, |
| 102 | + |
| 103 | + WRITE_C8_BYTES, 0x63, 4, // STV3&4 |
| 104 | + 0x3A, 0xE0, 0x5B, 0x56, // MAX=0x61 |
| 105 | + |
| 106 | + WRITE_C8_BYTES, 0x64, 6, // CLK_group1 |
| 107 | + 0x38, 0x0D, 0x72, 0xDD, |
| 108 | + 0x5B, 0x56, |
| 109 | + |
| 110 | + WRITE_C8_BYTES, 0x66, 6, // CLK_group1 |
| 111 | + 0x38, 0x11, 0x72, 0xE1, |
| 112 | + 0x5B, 0x56, |
| 113 | + |
| 114 | + WRITE_C8_BYTES, 0x68, 7, // FLC&FLV 1~2 |
| 115 | + 0x3B, 0x08, 0x08, 0x00, |
| 116 | + 0x08, 0x29, 0x5B, |
| 117 | + |
| 118 | + WRITE_C8_BYTES, 0x6E, 32, // gout_Mapping |
| 119 | + 0x00, 0x00, 0x00, 0x07, // gout4_swap_fw[4:0] |
| 120 | + 0x01, 0x13, 0x11, 0x0B, // gout8_swap_fw[4:0] |
| 121 | + 0x09, 0x16, 0x15, 0x1D, // gout12_swap_fw[4:0] |
| 122 | + 0x1E, 0x00, 0x00, 0x00, // gout16_swap_fw[4:0] |
| 123 | + 0x00, 0x00, 0x00, 0x1E, // gout20_swap_fw[4:0] |
| 124 | + 0x1D, 0x15, 0x16, 0x0A, // gout24_swap_fw[4:0] |
| 125 | + 0x0C, 0x12, 0x14, 0x02, // gout28_swap_fw[4:0] |
| 126 | + 0x08, 0x00, 0x00, 0x00, // gout32_swap_fw[4:0] |
| 127 | + |
| 128 | + WRITE_C8_D8, 0xBE, 0x11, // SOU_BIAS_FIX=1 |
| 129 | + |
| 130 | + WRITE_C8_BYTES, 0x6C, 7, // precharge GATE |
| 131 | + 0xCC, 0x0C, 0xCC, 0x84, |
| 132 | + 0xCC, 0x04, 0x50, |
| 133 | + |
| 134 | + WRITE_C8_D8, 0x7D, 0x72, |
| 135 | + WRITE_C8_D8, 0x7E, 0x38, // VGL_BT=1 5X (BT=0:6X) RT=0 |
| 136 | + |
| 137 | + WRITE_C8_BYTES, 0x70, 10, |
| 138 | + 0x02, 0x03, 0x09, 0x05, // vgh_clk |
| 139 | + 0x0C, 0x06, 0x09, 0x05, // vgh_clk_porch 0E |
| 140 | + 0x0C, 0x06, // vcl_clk_porch 0E |
| 141 | + |
| 142 | + WRITE_C8_BYTES, 0x90, 4, |
| 143 | + 0x06, 0x06, 0x05, 0x06, // bvdd_clk1_ad1 |
| 144 | + |
| 145 | + WRITE_C8_BYTES, 0x93, 3, |
| 146 | + 0x45, 0xFF, 0x00, |
| 147 | + |
| 148 | + // gamma start |
| 149 | + WRITE_C8_BYTES, 0xF0, 6, |
| 150 | + 0x45, 0x09, 0x08, 0x08, |
| 151 | + 0x26, 0x2A, |
| 152 | + |
| 153 | + WRITE_C8_BYTES, 0xF1, 6, |
| 154 | + 0x43, 0x70, 0x72, 0x36, |
| 155 | + 0x37, 0x6F, |
| 156 | + |
| 157 | + WRITE_C8_BYTES, 0xF2, 6, |
| 158 | + 0x45, 0x09, 0x08, 0x08, |
| 159 | + 0x26, 0x2A, |
| 160 | + |
| 161 | + WRITE_C8_BYTES, 0xF3, 6, |
| 162 | + 0x43, 0x70, 0x72, 0x36, |
| 163 | + 0x37, 0x6F, |
| 164 | + |
| 165 | + WRITE_COMMAND_8, GC9C01_SLPOUT, |
| 166 | + END_WRITE, |
| 167 | + |
| 168 | + DELAY, GC9C01_SLPOUT_DELAY, |
| 169 | + |
| 170 | + BEGIN_WRITE, |
| 171 | + WRITE_COMMAND_8, GC9C01_DISPON, // Display on |
| 172 | + END_WRITE, |
| 173 | + |
| 174 | + DELAY, 10}; |
| 175 | + |
| 176 | +class Arduino_GC9C01 : public Arduino_TFT |
| 177 | +{ |
| 178 | +public: |
| 179 | + Arduino_GC9C01( |
| 180 | + Arduino_DataBus *bus, int8_t rst = GFX_NOT_DEFINED, uint8_t r = 0, |
| 181 | + bool ips = false, int16_t w = GC9C01_TFTWIDTH, int16_t h = GC9C01_TFTHEIGHT, |
| 182 | + uint8_t col_offset1 = 0, uint8_t row_offset1 = 0, uint8_t col_offset2 = 0, uint8_t row_offset2 = 0); |
| 183 | + |
| 184 | + bool begin(int32_t speed = GFX_NOT_DEFINED) override; |
| 185 | + void writeAddrWindow(int16_t x, int16_t y, uint16_t w, uint16_t h) override; |
| 186 | + void setRotation(uint8_t r) override; |
| 187 | + void invertDisplay(bool) override; |
| 188 | + void displayOn() override; |
| 189 | + void displayOff() override; |
| 190 | + |
| 191 | +protected: |
| 192 | + void tftInit() override; |
| 193 | + |
| 194 | +private: |
| 195 | +}; |
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