[PowerPC] Fix issue with lowering byval parameters.

Lowering of byval parameters with sizes that are not represented by a single
store require multiple stores to properly address the correct size of the
parameter.

Sizes that cannot be done with a single store are 3 bytes, 5 bytes, 6 bytes,
7 bytes. It is not correct to simply perform an 8 byte store and for these
elements because then the store would be larger than the element and alias
analysis would assume that this is undefined behaivour and return NoAlias
for them.

This patch adds the correct stores so that the size of the store is not larger
than the size of the element.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D108795

Author: stefanp-synopsys

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -4369,21 +4369,10 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
           unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
           FuncInfo->addLiveInAttr(VReg, Flags);
           SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
-          SDValue Store;
-
-          if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
-            EVT ObjType = (ObjSize == 1 ? MVT::i8 :
-                           (ObjSize == 2 ? MVT::i16 : MVT::i32));
-            Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
-                                      MachinePointerInfo(&*FuncArg), ObjType);
-          } else {
-            // For sizes that don't fit a truncating store (3, 5, 6, 7),
-            // store the whole register as-is to the parameter save area
-            // slot.
-            Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
-                                 MachinePointerInfo(&*FuncArg));
-          }
-
+          EVT ObjType = EVT::getIntegerVT(*DAG.getContext(), ObjSize * 8);
+          SDValue Store =
+              DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
+                                MachinePointerInfo(&*FuncArg), ObjType);
           MemOps.push_back(Store);
         }
         // Whether we copied from a register or not, advance the offset

llvm/test/CodeGen/PowerPC/jaggedstructs.ll

@@ -18,10 +18,21 @@ entry:
   ret void
 }
 
-; CHECK-DAG: std 3, 160(1)
-; CHECK-DAG: std 6, 184(1)
-; CHECK-DAG: std 5, 176(1)
-; CHECK-DAG: std 4, 168(1)
+; CHECK-LABEL: test
+; CHECK:     stb 6, 191(1)
+; CHECK:     rldicl 7, 6, 56, 8
+; CHECK:     sth 7, 189(1)
+; CHECK:     rldicl 6, 6, 40, 24
+; CHECK:     stw 6, 185(1)
+; CHECK:     sth 5, 182(1)
+; CHECK:     rldicl 5, 5, 48, 16
+; CHECK:     stw 5, 178(1)
+; CHECK:     stb 4, 175(1)
+; CHECK:     rldicl 4, 4, 56, 8
+; CHECK:     stw 4, 171(1)
+; CHECK:     stb 3, 167(1)
+; CHECK:     rldicl 3, 3, 56, 8
+; CHECK:     sth 3, 165(1)
 ; CHECK-DAG: lbz {{[0-9]+}}, 167(1)
 ; CHECK-DAG: lhz {{[0-9]+}}, 165(1)
 ; CHECK-DAG: stb {{[0-9]+}}, 55(1)