Update kernel to 6.12.44 base on 3.0-dev branch (open-edge-platform#430)

Signed-off-by: sys_oak <sys_oak@intel.com>
Co-authored-by: sys_oak <sys_oak@intel.com>

Author: renjiaox

SPECS/kernel-headers/kernel-headers.signatures.json

@@ -1,5 +1,5 @@
 {
   "Signatures": {
-    "lts-v6.12.39-emt-250721T212915Z.tar.gz": "10747ca512fe0a07eb19d6c40d3ec2edea7a17b1fd232214d6d279c29a054f6a"
+    "linux-6.12.44.tar.gz": "fac0ed5371cbd46ebc8a2a1e152ac5fbb5fc2660e748a7fc1d28b8e399854a1a"
   }
 }

SPECS/kernel-headers/kernel-headers.spec

@@ -13,14 +13,14 @@
 
 Summary:        Linux API header files
 Name:           kernel-headers
-Version:        6.12.39
+Version:        6.12.44
 Release:        1%{?dist}
 License:        GPLv2
 Vendor:         Intel Corporation
 Distribution:   Edge Microvisor Toolkit
 Group:          System Environment/Kernel
-URL:            https://github.com/intel/linux-intel-lts
-Source0:        https://github.com/intel/linux-intel-lts/archive/refs/tags/lts-v6.12.39-emt-250721T212915Z.tar.gz
+URL:            https://www.kernel.org/pub/linux/kernel
+Source0:        https://www.kernel.org/pub/linux/kernel/v6.x/linux-6.12.44.tar.gz
 # Historical name shipped by other distros
 Provides:       glibc-kernheaders = %{version}-%{release}
 BuildArch:      noarch
@@ -41,7 +41,7 @@ cross-glibc package.
 %endif
 
 %prep
-%setup -q -n lts-v6.12.39-emt-250721T212915Z
+%setup -q -n linux-6.12.44
 
 %build
 make mrproper
@@ -76,6 +76,9 @@ done
 %endif
 
 %changelog
+* Tue Sep 09 2025 Ren Jiaojiao <jiaojiaox.ren@intel.com> - 6.12.44-1
+- Update kernel to 6.12.44
+
 * Thu Jul 24 2025 Ren Jiaojiao <jiaojiaox.ren@intel.com> - 6.12.39-1
 - Update kernel to 6.12.39
 

SPECS/kernel-rt/0001-Add-security.md-file.misc

@@ -0,0 +1,27 @@
+From 3a01e64f0d80c5154743e5c304774066ceb10972 Mon Sep 17 00:00:00 2001
+From: Lili Li <lili.li@intel.com>
+Date: Tue, 24 Oct 2023 10:33:36 +0800
+Subject: [PATCH] Add security.md file
+
+Add security.md file to open source repository.
+
+Signed-off-by: Lili Li <lili.li@intel.com>
+---
+ security.md | 5 +++++
+ 1 file changed, 5 insertions(+)
+ create mode 100644 security.md
+
+diff --git a/security.md b/security.md
+new file mode 100644
+index 0000000000000..b6eefdf389795
+--- /dev/null
++++ b/security.md
+@@ -0,0 +1,5 @@
++Security Policy
++Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation.
++
++Reporting a Vulnerability
++Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html).
+-- 
+2.25.1
+

SPECS/kernel-rt/0001-Added-spi_set_cs-for-more-stable-r-w-operations-in-S.lpss

@@ -0,0 +1,72 @@
+From a5a73973d12960de08a3b4cb623d7161b20c3527 Mon Sep 17 00:00:00 2001
+From: Atapasex <amardeepx.tapase@intel.com>
+Date: Tue, 21 Jan 2025 11:20:08 +0530
+Subject: [PATCH 2/6] Added spi_set_cs() for more stable r/w operations in SPI
+ Mode 3 -TWL
+
+Signed-off-by: Atapasex <amardeepx.tapase@intel.com>
+---
+ drivers/spi/spi-pxa2xx.c | 4 ++++
+ drivers/spi/spi.c        | 3 ++-
+ include/linux/spi/spi.h  | 2 ++
+ 3 files changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
+index bf1f34b0ffc8e..878ec83feaca2 100644
+--- a/drivers/spi/spi-pxa2xx.c
++++ b/drivers/spi/spi-pxa2xx.c
+@@ -1055,6 +1055,8 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
+ 	if (!pxa25x_ssp_comp(drv_data))
+ 		pxa2xx_spi_write(drv_data, SSTO, TIMOUT_DFLT);
+ 
++	spi_set_cs(spi, false, false);
++
+ 	/* First set CR1 without interrupt and service enables */
+ 	pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
+ 
+@@ -1064,6 +1066,8 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
+ 	/* Restart the SSP */
+ 	pxa_ssp_enable(drv_data->ssp);
+ 
++	spi_set_cs(spi, true, false);
++
+ 	if (is_mmp2_ssp(drv_data)) {
+ 		u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
+ 
+diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
+index 0f3e6e2c24743..e2ee9627336b1 100644
+--- a/drivers/spi/spi.c
++++ b/drivers/spi/spi.c
+@@ -1074,7 +1074,7 @@ static void spi_toggle_csgpiod(struct spi_device *spi, u8 idx, bool enable, bool
+ 		spi_delay_exec(&spi->cs_inactive, NULL);
+ }
+ 
+-static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
++void spi_set_cs(struct spi_device *spi, bool enable, bool force)
+ {
+ 	bool activate = enable;
+ 	u8 idx;
+@@ -1129,6 +1129,7 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
+ 			spi_delay_exec(&spi->cs_inactive, NULL);
+ 	}
+ }
++EXPORT_SYMBOL_GPL(spi_set_cs);
+ 
+ #ifdef CONFIG_HAS_DMA
+ static int spi_map_buf_attrs(struct spi_controller *ctlr, struct device *dev,
+diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
+index 4b95663163e0b..c5e9bef5d03d8 100644
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -811,6 +811,8 @@ extern int spi_controller_resume(struct spi_controller *ctlr);
+ extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr);
+ extern void spi_finalize_current_message(struct spi_controller *ctlr);
+ extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
++/* SPI driver calls this function to assert/deassert the chip select */
++extern void spi_set_cs(struct spi_device *spi, bool enable, bool force);
+ 
+ /* Helper calls for driver to timestamp transfer */
+ void spi_take_timestamp_pre(struct spi_controller *ctlr,
+-- 
+2.25.1
+

SPECS/kernel-rt/0001-EDAC-ie31200-Add-two-Intel-SoCs-for-EDAC-support.edac

@@ -0,0 +1,43 @@
+From ed20e3ad5cce3759718c722b6b9f1589cf0656f3 Mon Sep 17 00:00:00 2001
+From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
+Date: Tue, 22 Apr 2025 21:44:50 +0800
+Subject: [PATCH 1/2] EDAC/ie31200: Add two Intel SoCs for EDAC support
+
+Add two compute die IDs for Raptor Lake-S and Alder Lake-S for EDAC
+support. Note that because Alder Lake-S shares the same memory controller
+registers as Raptor Lake-S, it can reuse the configuration data of Raptor
+Lake-S for EDAC support.
+
+Tested-by: James Jernigan <jameswestonjernigan@gmail.com>
+Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
+---
+ drivers/edac/ie31200_edac.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
+index 2048341495798..55cf54741aa0b 100644
+--- a/drivers/edac/ie31200_edac.c
++++ b/drivers/edac/ie31200_edac.c
+@@ -89,6 +89,10 @@
+ #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1	0xa703
+ #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2	0x4640
+ #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3	0x4630
++#define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4	0xa700
++
++/* Alder Lake-S */
++#define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1	0x4660
+ 
+ #define IE31200_RANKS_PER_CHANNEL	8
+ #define IE31200_DIMMS_PER_CHANNEL	2
+@@ -734,6 +738,8 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
+ 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1), (kernel_ulong_t)&rpl_s_cfg},
+ 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2), (kernel_ulong_t)&rpl_s_cfg},
+ 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3), (kernel_ulong_t)&rpl_s_cfg},
++	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4), (kernel_ulong_t)&rpl_s_cfg},
++	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1), (kernel_ulong_t)&rpl_s_cfg},
+ 	{ 0, } /* 0 terminated list. */
+ };
+ MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
+-- 
+2.34.1
+