Fix spelling (#6)

Thank you.

Author: jbampton

README.md

@@ -46,6 +46,6 @@ This document, excluding specifically indicated sections, is distributed under t
 ![CC BY 4.0](https://licensebuttons.net/l/by/4.0/88x31.png)
 </a>
 
-Copyright (C) 2023 mruby forum commitiee.  
+Copyright (C) 2023 mruby forum committee.  
 Copyright (C) 2023 Kyushu Institute of Technology.  
 Copyright (C) 2023 Shimane IT Open-Innovation Center.  

mruby_io_SPI_en.md

@@ -35,12 +35,12 @@ spi = SPI.new( unit:1, frequency:10_000_000 )
 
 mode parameter
 
-| mode | CPOL | CPHA | Idle state clock polarity | Sampling timming | |
-|:----:|:----:|:----:|:-------------------------:|:----------------:|-|
-|   0  |  0   |  0   | Low                       | Rising edge      |![mode0](img/spi_mode0.png)|
-|   1  |  0   |  1   | Low                       | Falling edge     |![mode1](img/spi_mode1.png)|
-|   2  |  1   |  0   | High                      | Falling edge     |![mode2](img/spi_mode2.png)|
-|   3  |  1   |  1   | High                      | Rising edge      |![mode3](img/spi_mode3.png)|
+| mode | CPOL | CPHA | Idle state clock polarity | Sampling timing | |
+|:----:|:----:|:----:|:-------------------------:|:---------------:|-|
+|   0  |  0   |  0   | Low                       |   Rising edge   |![mode0](img/spi_mode0.png)|
+|   1  |  0   |  1   | Low                       |  Falling edge   |![mode1](img/spi_mode1.png)|
+|   2  |  1   |  0   | High                      |  Falling edge   |![mode2](img/spi_mode2.png)|
+|   3  |  1   |  1   | High                      |   Rising edge   |![mode3](img/spi_mode3.png)|
 
 
 Device-specific

mruby_io_SPI_ja.md

@@ -35,12 +35,12 @@ spi = SPI.new( unit:1, frequency:10_000_000 )
 
 モードパラメータ
 
-| mode | CPOL | CPHA | Idle state clock polarity | Sampling timming | |
-|:----:|:----:|:----:|:-------------------------:|:----------------:|-|
-|   0  |  0   |  0   | Low                       | Rising edge      |![mode0](img/spi_mode0.png)|
-|   1  |  0   |  1   | Low                       | Falling edge     |![mode1](img/spi_mode1.png)|
-|   2  |  1   |  0   | High                      | Falling edge     |![mode2](img/spi_mode2.png)|
-|   3  |  1   |  1   | High                      | Rising edge      |![mode3](img/spi_mode3.png)|
+| mode | CPOL | CPHA | Idle state clock polarity | Sampling timing | |
+|:----:|:----:|:----:|:-------------------------:|:---------------:|-|
+|   0  |  0   |  0   | Low                       |   Rising edge   |![mode0](img/spi_mode0.png)|
+|   1  |  0   |  1   | Low                       |  Falling edge   |![mode1](img/spi_mode1.png)|
+|   2  |  1   |  0   | High                      |  Falling edge   |![mode2](img/spi_mode2.png)|
+|   3  |  1   |  1   | High                      |   Rising edge   |![mode3](img/spi_mode3.png)|
 
 
 機種依存