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lines changed Original file line number Diff line number Diff line change @@ -21,6 +21,7 @@ Install it from [VS Code Marketplace](https://marketplace.visualstudio.com/items
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- Vivado UCF constraints
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- Synopsys Design Constraints
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- Verilog Filelists (dot-F files)
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+ - Tcl
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- Simple Snippets
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- Linting support from:
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- Icarus Verilog - ` iverilog `
@@ -321,3 +322,5 @@ You can check it by opening the **Output** pane in VS Code and choose _Verilog_
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- [ ericsonj/verilog-format] ( https://github.com/ericsonj/verilog-format )
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- [ thomasrussellmurphy/istyle-verilog-formatter] ( https://github.com/thomasrussellmurphy/istyle-verilog-formatter )
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- [ slang C++ docs] ( https://sv-lang.com/ )
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+ - [ bitwisecook/vscode-tcl: Tcl for Visual Studio Code] ( https://github.com/bitwisecook/vscode-tcl )
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+ - ` configs/tcl.configuration.json ` and ` syntaxes/tcl.tmlanguage.json ` are obtained from the repo.
Original file line number Diff line number Diff line change
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+ {
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+ "capabilities" : {
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+ "documentOnTypeFormattingProvider" : {
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+ "firstTriggerCharacter" : " }" ,
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+ "moreTriggerCharacter" : [
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+ " ;" ,
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+ " ,"
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+ ]
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+ },
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+ "documentRangeFormattingProvider" : " true" ,
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+ "renameProvider" : " true" ,
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+ "documentHighlightProvider" : " true" ,
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+ "referencesProvider" : " true"
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+ },
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+ "comments" : {
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+ // symbol used for single line comment. Remove this entry if your language does not support line comments
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+ "lineComment" : " #"
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+ },
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+ // symbols used as brackets
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+ "brackets" : [
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+ [
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+ " {" ,
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+ " }"
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+ ],
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+ [
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+ " [" ,
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+ " ]"
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+ ],
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+ [
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+ " (" ,
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+ " )"
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+ ]
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+ ],
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+ // symbols that are auto closed when typing
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+ "autoClosingPairs" : [
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+ {
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+ "open" : " {" ,
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+ "close" : " }"
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+ },
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+ {
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+ "open" : " [" ,
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+ "close" : " ]"
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+ },
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+ {
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+ "open" : " (" ,
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+ "close" : " )"
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+ },
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+ {
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+ "open" : " \" " ,
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+ "close" : " \" " ,
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+ "notIn" : [
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+ " string"
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+ ]
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+ }
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+ ],
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+ // symbols that that can be used to surround a selection
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+ "surroundingPairs" : [
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+ [
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+ " {" ,
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+ " }"
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+ ],
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+ [
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+ " [" ,
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+ " ]"
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+ ],
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+ [
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+ " (" ,
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+ " )"
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+ ],
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+ [
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+ " \" " ,
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+ " \" "
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+ ]
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+ ]
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+ }
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" onLanguage:bsv" ,
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" onLanguage:vhdl" ,
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" onLanguage:ucf" ,
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+ " onLanguage:tcl" ,
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" onLanguage:sdc" ,
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" onLanguage:xdc" ,
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" onLanguage:verilog-filelist"
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],
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"configuration" : " ./configs/sdc.configuration.json"
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},
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+ {
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+ "id" : " tcl" ,
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+ "aliases" : [
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+ " Tcl" ,
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+ " tcl"
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+ ],
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+ "extensions" : [
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+ " .tcl" ,
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+ " tm" ,
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+ " tk"
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+ ],
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+ "configuration" : " ./configs/tcl.configuration.json"
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+ },
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{
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"id" : " xdc" ,
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"aliases" : [
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"scopeName" : " source.sdc" ,
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"path" : " ./syntaxes/sdc.tmLanguage.json"
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},
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+ {
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+ "language" : " tcl" ,
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+ "scopeName" : " source.tcl" ,
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+ "path" : " ./syntaxes/tcl.tmlanguage.json"
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+ },
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{
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"language" : " xdc" ,
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"scopeName" : " source.sdc" ,
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