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1 parent b19d3f8 commit 7ab82deCopy full SHA for 7ab82de
syntaxes/verilog.tmLanguage.json
@@ -105,7 +105,7 @@
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"include": "#keywords"
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},
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{
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- "begin": "^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if)\\s*(?=\\(|$)",
+ "begin": "^\\s*(?!always|and|assign|output|input|inout|wire|module)([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if)\\s*(?=\\(|$)",
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"beginCaptures": {
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"1": {
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"name": "entity.name.tag.module.reference.verilog"
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