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Added on v1.26.0 |
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i recently switched to vscode to check it out as a new editor for verilog.
the features added by the verilog-hdl-support extension look quite nice, but there is one thing i'm missing. maybe, i just missed something in the configuration or need to install something else in addition.
i would like to see a hierarchical view of my design, i.e. for each module, i see what other modules are instantiated within, showing a tree structure which allows me to get an overview of the design, allowing me to dive into the structure.
how can this be shown within vscode-verilog-hdl-support or what else do i need to add?
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